COP8SG National Semiconductor, COP8SG Datasheet - Page 43

• Manufacturer Part Number: COP8SG
• Description: 8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory/ Two Comparators and USART
• Manufacturer: National Semiconductor

12.0 MICROWIRE/PLUS
12.1.2 MICROWIRE/PLUS Slave Mode Operation
In the MICROWIRE/PLUS Slave mode of operation the SK
clock is generated by an external source. Setting the MSEL
bit in the CNTRL register enables the SO and SK functions
onto the G Port. The SK pin must be selected as an input
and the SO pin is selected as an output pin by setting and re-
setting the appropriate bits in the Port G configuration regis-
ter. Table 11 summarizes the settings required to enter the
Slave mode of operation.
SK Phase
This table assumes that the control flag MSEL is set.
Config. Bit
Alternate
Alternate
Normal
Normal
G4 (SO)
TABLE 11. MICROWIRE/PLUS Mode Settings
1
0
1
0
FIGURE 31. MICROWIRE/PLUS SPI Mode Interface Timing, Alternate SK Mode, SK Idle Phase being Low
FIGURE 30. MICROWIRE/PLUS SPI Mode Interface Timing, Normal SK Mode, SK Idle Phase being Low
Config. Bit
G5 (SK)
1
1
0
0
G6 (SKSEL)
Config. Bit
TABLE 12. MICROWIRE/PLUS Shift Clock Polarity and Sample/Shift Phase
STATE
STATE
0
1
0
1
Fun.
TRI-
TRI-
G4
SO
SO
Port G
Fun.
Ext.
Ext.
G5
Int.
SK
Int.
SK
SK
SK
(Continued)
MICROWIRE/PLUS
Master
MICROWIRE/PLUS
Master
MICROWIRE/PLUS
Slave
MICROWIRE/PLUS
Slave
G5 Data
Operation
Bit
0
0
1
1
SO Clocked Out
SK Falling Edge
SK Falling Edge
SK Rising Edge
SK Rising Edge
43
The user must set the BUSY flag immediately upon entering
the Slave mode. This ensures that all data bits sent by the
Master is shifted properly. After eight clock pulses the BUSY
flag is clear, the shift clock is stopped, and the sequence
may be repeated.
12.1.3 Alternate SK Phase Operation and SK Idle
Polarity
The device allows either the normal SK clock or an alternate
phase SK clock to shift data in and out of the SIO register. In
both the modes the SK idle polarity can be either high or low.
The polarity is selected by bit 5 of Port G data register. In the
normal mode data is shifted in on the rising edge of the SK
clock and the data is shifted out on the falling edge of the SK
clock. In the alternate SK phase operation, data is shifted in
on the falling edge of the SK clock and shifted out on the ris-
ing edge of the SK clock. Bit 6 of Port G configuration regis-
ter selects the SK edge.
A control flag, SKSEL, allows either the normal SK clock or
the alternate SK clock to be selected. Resetting SKSEL
causes the MICROWIRE/PLUS logic to be clocked from the
normal SK signal. Setting the SKSEL flag selects the alter-
nate SK clock. The SKSEL is mapped into the G6 configura-
tion bit. The SKSEL flag will power up in the reset condition,
selecting the normal SK signal.
On:
SI Sampled On:
SK Falling Edge
SK Falling Edge
SK Rising Edge
SK Rising Edge
DS101317-33
DS101317-34
www.national.com
Phase
SK Idle
High
High
Low
Low