COP8SG National Semiconductor, COP8SG Datasheet - Page 33

• Manufacturer Part Number: COP8SG
• Description: 8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory/ Two Comparators and USART
• Manufacturer: National Semiconductor

9.0 Comparators
The device contains two differential comparators, each with
a pair of inputs (positive and negative) and an output. Ports
F1–F3 and F4–F6 are used for the comparators. The follow-
ing is the Port F assignment:
CMPSL REGISTER (ADDRESS X’00B7)
The CMPSL register contains the following bits:
Reserved These bits are reserved and must be zero
CMP20E
CMP2RD Comparator 2 result (this is a read only bit, which
CMP2EN Enable comparator 2
CMP10E
CMP1RD Comparator 1 result (this is a read only bit, which
CMP1EN Enable comparator 1
Note that the two unused bits of CMPSL may be used as
software flags.
Note: For compatibility with existing code and with existing Mask ROMMed
F6 Comparator2 output
F5 Comparator2 positive input
F4 Comparator2 negative input
F3 Comparator1 output
F2 Comparator1 positive input
F1 Comparator1 negative input
Reserved
devices the bits of the CMPSL register will take precedence over the
associated Port F configuration and data output bits.
Bit 7
Selects pin I6 as comparator 2 output provided
that CMP2EN is set to enable the comparator
will read as 0 if the comparator is not enabled)
Selects pin I3 as comparator 1 output provided
that CMPIEN is set to enable the comparator
will read as 0 if the comparator is not enabled)
CMP20E
CMP2RD
FIGURE 26. Interrupt Block Diagram
CMP2EN
33
CMP10E
A Comparator Select Register (CMPSL) is used to enable
the comparators, read the outputs of the comparators inter-
nally, and enable the outputs of the comparators to the pins.
Two control bits (enable and output enable) and one result
bit are associated with each comparator. The comparator re-
sult bits (CMP1RD and CMP2RD) are read only bits which
will read as zero if the associated comparator is not enabled.
The Comparator Select Register is cleared with reset, result-
ing in the comparators being disabled. The comparators
should also be disabled before entering either the HALT or
IDLE modes in order to save power. The configuration of the
CMPSL register is as follows:
10.0 Interrupts
10.1 INTRODUCTION
Each device supports thirteen vectored interrupts. Interrupt
sources include Timer 0, Timer 1, Timer 2, Timer 3, Port L
Wakeup, Software Trap, MICROWIRE/PLUS, and External
Input.
All interrupts force a branch to location 00FF Hex in program
memory. The VIS instruction may be used to vector to the
appropriate service routine from location 00FF Hex.
The Software trap has the highest priority while the default
VIS has the lowest priority.
Each of the 13 maskable inputs has a fixed arbitration rank-
ing and vector.
Figure 26 shows the Interrupt Block Diagram.
CMP1RD
CMP1EN
DS101317-28
Reserved
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Bit 0