XC68HC705JJ7 Motorola, XC68HC705JJ7 Datasheet - Page 87

• Manufacturer Part Number: XC68HC705JJ7
• Description: MICROCONTROLLER
• Manufacturer: Motorola

7.3.3 Pulldown Register A
MC68HC705JJ7 • MC68HC705JP7 — REV 4
MOTOROLA
Address:
All port A pins can have software programmable pulldown devices
enabled or disabled globally by SWPDI bit in the MOR. These pulldown
devices are controlled by the write-only pulldown register A (PDRA)
shown in
on the pulldown devices if the port A pin is an input. Reading the PDRA
returns undefined results since it is a write-only register; therefore, do
not change the value in PDRA with read/modify/write instructions. On
the MC68HC705JP7 the PDRA contains two pulldown control bits
(PDICH and PDICL) for port C. Reset clears the PDIA5–PDIA0, PDICH,
and PDICL bits, which turns on all the port A and port C pulldown
devices.
PDICH — Upper Port C Pulldown Inhibit Bits (MC68HC705JP7)
PDICL — Lower Port C Pulldown Inhibit Bits (MC68HC705JP7)
Reset:
Read:
Write:
Writing to this write-only bit controls the port C pulldown devices on
the upper four bits (PC4–PC7). Reading these pulldown register A
bits returns undefined data. Reset clears bit PDICH.
Writing to this write-only bit controls the port C pulldown devices on
the lower four bits (PC0–PC3). Reading these pulldown register A bits
returns undefined data. Reset clears bit PDICL.
1 = Upper four port C pins pulldown devices turned off
0 = Upper four port C pins pulldown devices turned on if pin has
1 = Lower four port C pins pulldown devices turned off
$0010
PDICH
Bit 7
Figure
been programmed by the DDRC to be an input
0
Figure 7-3. Pulldown Register A (PDRA)
Parallel Input/Output
PDICL
= Unimplemented
7-3. Clearing the PDIA5–PDIA0 bits in the PDRA turns
6
0
PDIA5
5
0
PDIA4
4
0
PDIA3
3
0
PDIA2
2
0
Advance Information
Parallel Input/Output
PDIA1
1
0
PDIA0
Bit 0
Port A
0
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