XC68HC705JJ7 Motorola, XC68HC705JJ7 Datasheet - Page 157

• Manufacturer Part Number: XC68HC705JJ7
• Description: MICROCONTROLLER
• Manufacturer: Motorola

MC68HC705JJ7 • MC68HC705JP7 — REV 4
MOTOROLA
NOTE:
COPC — COP Clear Bit
If the voltage on the IRQ/V
turns off and remains off until the IRQ/V
1.5
Less than 1.5
Less than 1.5
Less than 1.5
More than 1.5
1. The SWAIT bit in the MOR converts STOP instructions to HALT instructions.
2. Reset the COP watchdog immediately before executing the WAIT/HALT instruction.
3. Don’t care
This write-only bit resets the COP watchdog. The COP watchdog is
active in the run, wait, and halt modes of operation if the COP is
enabled by setting the COPEN bit in the MOR. The STOP instruction
disables the COP watchdog by clearing the counter and turning off its
clock source.
In applications that depend on the COP watchdog, the STOP
instruction can be disabled by setting the SWAIT bit in the MOR. In
applications that have wait cycles longer than the COP timeout
period, the COP watchdog can be disabled by clearing the COPEN
bit.
and disabling the COP watchdog.
IRQ/V
Voltage on
V
Table 10-2
DD
PP
.
Table 10-2. COP Watchdog Recommendations
Pin
V
V
V
V
DD
DD
DD
DD
summarizes recommended conditions for enabling
Core Timer
(in MOR)
SWAIT
X
1
1
0
PP
pin exceeds 1.5
(1)
Greater than COP
Wait/Halt Time
Less than COP
timeout period
timeout period
X
X
PP
(3)
(3)
pin voltage falls below
V
DD
, the COP watchdog
Watchdog Condition
Recommended COP
Advance Information
Enabled
Disabled
Disabled
Disabled
COP Watchdog
Core Timer
(2)
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