XC68HC705JJ7 Motorola, XC68HC705JJ7 Datasheet - Page 147

• Manufacturer Part Number: XC68HC705JJ7
• Description: MICROCONTROLLER
• Manufacturer: Motorola

MC68HC705JJ7 • MC68HC705JP7 — REV 4
MOTOROLA
SPIR — Serial Peripheral Interrupt Reset Bit
CPHA — Clock Phase Bit
SPR0:1 — Serial Peripheral Clock Rate Select Bits
The SPIR bit is a write-only control to reset the SPIF flag bit in the
SSR. Reading the SPIR bit will return a logic 0.
The CPHA bit controls the clock timing and phase in the SIOP. Data
is changed on the falling edge of SCK and data is captured (read) on
the rising edge of SCK. This bit is cleared by reset.
The SPR0 and SPR1 bits select one of four clock rates given in
Table 9-1
configured with the SIOP as a master (MSTR = 1). The fastest rate is
when both SPR0 and SPR1 are set. Both the SPR0 and SPR1 bits
are cleared by reset, which places the SIOP clock selection at the
slowest rate.
1 = Reset the SPIF flag bit
0 = No effect
1 = SCK is idle low
0 = SCK is idle high
Simple Synchronous Serial Interface
SPR1
0
0
1
1
to be supplied on the PB7/SCK pin when the device is
Table 9-1. SIOP Clock Rate Selection
SPR0
0
1
0
1
Oscillator Frequency
Simple Synchronous Serial Interface
SIOP Clock Rate
Divided by:
64
32
16
8
Advance Information
SIOP Registers
147