XC68HC705JJ7 Motorola, XC68HC705JJ7 Datasheet - Page 170
XC68HC705JJ7
Manufacturer Part Number
XC68HC705JJ7
Description
MICROCONTROLLER
Manufacturer
Motorola
Datasheet
1.XC68HC705JJ7.pdf
(242 pages)
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Programmable Timer
11.7 Timer Control Register
Advance Information
170
Address:
The timer control register (TCR) shown in
following functions:
Reset clears all the bits in the TCR with the exception of the IEDG bit
which is unaffected.
ICIE — Input Capture Interrupt Enable Bit
OCIE — Output Compare Interrupt Enable Bit
Reset:
Read:
Write:
•
•
•
•
•
This read/write bit enables interrupts caused by an active signal on
the TCAP pin or from CPF2 flag bit of the analog subsystem voltage
comparator 2. Reset clears the ICIE bit.
This read/write bit enables interrupts caused by an active match of the
output compare function. Reset clears the OCIE bit.
1 = Input capture interrupts enabled
0 = Input capture interrupts disabled
1 = Output compare interrupts enabled
0 = Output compare interrupts disabled
Enables input capture interrupts
Enables output compare interrupts
Enables timer overflow interrupts
Controls the active edge polarity of the TCAP signal
Controls the active level of the TCMP output
$0012
Bit 7
ICIE
0
Figure 11-10. Timer Control Register (TCR)
Programmable Timer
= Unimplemented
OCIE
6
0
TOIE
5
0
MC68HC705JJ7 • MC68HC705JP7 — REV 4
4
0
0
U = Unaffected
Figure
3
0
0
11-10, performs the
2
0
0
IEDG
U
1
MOTOROLA
OLVL
Bit 0
0
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