XC68HC705JJ7 Motorola, XC68HC705JJ7 Datasheet - Page 70

• Manufacturer Part Number: XC68HC705JJ7
• Description: MICROCONTROLLER
• Manufacturer: Motorola

Resets
5.5.3 Low-Voltage Reset (LVR)
5.5.4 Illegal Address Reset
5.6 Reset States
5.6.1 CPU
Advance Information
70
NOTE:
The LVR activates the RST reset signal to reset the device when the
voltage on the V
assert the pulldown device to pull the RESET pin low for three to four
cycles of the internal bus.
The LVR reset function can be enabled or disabled by programming the
LVREN bit in the MOR.
The LVR is intended for applications where the V
normally operates above 4.5 volts.
An opcode fetch (execution of an instruction) at an address that is not in
the EPROM (locations $0700–$1FFF) or the RAM (locations
$0020–$00FF) generates an illegal address reset. The illegal address
reset will assert the pulldown device to pull the RESET pin low for three
to four cycles of the internal bus.
This subsection describe how the various resets initialize the MCU.
A reset has these effects on the CPU:
•
•
•
•
•
Loads the stack pointer with $FF
Sets the I bit in the condition code register, inhibiting interrupts
Loads the program counter with the user-defined reset vector from
locations $1FFE and $1FFF
Clears the stop latch, enabling the CPU clock
Clears the wait latch, bringing the CPU out of the wait mode
DD
pin falls below the LVR trip voltage. The LVR will
Resets
MC68HC705JJ7 • MC68HC705JP7 — REV 4
DD
supply voltage
MOTOROLA