XC68HC705JJ7 Motorola, XC68HC705JJ7 Datasheet - Page 58

• Manufacturer Part Number: XC68HC705JJ7
• Description: MICROCONTROLLER
• Manufacturer: Motorola

Interrupts
4.6.3 IRQ Status and Control Register (ISCR)
Advance Information
58
Address:
IRQ/V
PA0:3 pins have returned to a low level. Similarly, if the IRQ/V
at a low level, the PA0:3 pins will be ignored until the IRQ/V
to a high state.
The IRQ status and control register (ISCR), shown in Figure 4-4,
contains an external interrupt mask (IRQE), an external interrupt flag
(IRQF), and a flag reset bit (IRQR). Unused bits will read as logic 0s. The
ISCR also contains two control bits for the oscillators, external pin
oscillator, and internal low-power oscillator. Reset sets the IRQE and
OM2 bits and clears all the other bits.
IRQE — External Interrupt Request Enable Bit
OM1 and OM2 — Oscillator Select Bits
Reset:
Read:
Write:
This read/write bit enables external interrupts. Reset sets the IRQE
bit.
These bits control the selection and enabling of the oscillator source
for the MCU. One choice is the internal low-power oscillator (LPO).
The other choice is the external pin oscillator (EPO) which is common
to most M68HC05 MCU devices. The EPO uses external components
1 = External interrupt processing enabled
0 = External interrupt processing disabled
PP
$000D
Figure 4-4. IRQ Status and Control Register (ISCR)
IRQE
Bit 7
pin and other PA0:3 pins are to be ignored until ALL of the
1
= Unimplemented
OM2
6
1
Interrupts
OM1
5
0
MC68HC705JJ7 • MC68HC705JP7 — REV 4
R
R
4
0
0
= Reserved
IRQF
3
0
2
0
0
U = Unaffected
IRQR
PP
U
1
0
pin returns
MOTOROLA
PP
pin is
Bit 0
0
0