AT83EC5123 ATMEL Corporation, AT83EC5123 Datasheet - Page 86

• Manufacturer Part Number: AT83EC5123
• Description: (AT8xx512x) Smart Card Reader ICs
• Manufacturer: ATMEL Corporation

86
AT8xC5122/23
Table 69. USB Endpoint Interrupt Register - UEPINT (S:F8h read-only)
Reset Value = 0000 0000b
Number
Bit
7
6
5
4
3
2
1
0
7
-
Mnemonic Description
EP6INT
EP5INT
EP4INT
EP3INT
EP2INT
EP1INT
EP0INT
EP6INT
Bit
-
6
Reserved
The value read from these bits is always 0. Do not change this bit.
Endpoint 6 Interrupt
This bit is set by hardware when an interrupt is triggered by the (see Table 65 on
page 83) and this endpoint interrupt is enabled by the UEPIEN Register (see Table
70 on page 87).
This bit is cleared by hardware.
Endpoint 5 Interrupt
This bit is set by hardware when an interrupt is triggered by the UEPSTAX Register
(see Table 65 on page 83) and this endpoint interrupt is enabled by the UEPIEN
Register (see Table 70 on page 87).
This bit is cleared by hardware.
Endpoint 4 Interrupt
This bit is set by hardware when an interrupt is triggered by the UEPSTAX Register
(see Table 65 on page 83) and this endpoint interrupt is enabled by the UEPIEN
Register (see Table 70 on page 87).
This bit is cleared by hardware.
Endpoint 3 Interrupt
This bit is set by hardware when an interrupt is triggered by the UEPSTAX Register
(see Table 65 on page 83) and this endpoint interrupt is enabled by the UEPIEN
Register (see Table 70 on page 87).
This bit is cleared by hardware.
Endpoint 2 Interrupt
This bit is set by hardware when an interrupt is triggered by the UEPSTAX Register
(see Table 65 on page 83) and this endpoint interrupt is enabled by the UEPIEN
Register (see Table 70 on page 87).
This bit is cleared by hardware.
Endpoint 1 Interrupt
This bit is set by hardware when an interrupt is triggered by the UEPSTAX Register
(see Table 65 on page 83) and this endpoint interrupt is enabled by the UEPIEN
Register (see Table 70 on page 87).
This bit is cleared by hardware.
Endpoint 0 Interrupt
This bit is set by hardware when an interrupt is triggered by the UEPSTAX Register
(see Table on page 83) and this endpoint interrupt is enabled by the UEPIEN
Register (see Table 70 on page 87).
This bit is cleared by hardware.
EP5INT
5
EP4INT
4
EP3INT
3
EP2INT
2
EP1INT
1
4202B–SCR–07/03
EP0INT
0