AT83EC5123 ATMEL Corporation, AT83EC5123 Datasheet - Page 54

• Manufacturer Part Number: AT83EC5123
• Description: (AT8xx512x) Smart Card Reader ICs
• Manufacturer: ATMEL Corporation

DC/DC Converter
Configuration
54
AT8xC5122/23
Table 55. Smart Card Clock Reload Register - SCICLK (S:C1h, SCRS=1)
Reset Value = 0X10 1111b (default value for a divider by two)
The Smart Card voltage (CVCC) is supplied by the integrated DC/DC converter which is
controlled by several registers:
•
•
•
The DC/DC converter cannot be switched on while the CPRES pin remains inactive. If
CPRES pin becomes inactive while the DC/DC converter is operating an automatic shut
down sequence of the DC/DC converter is initiated by the electronics.
It is mandatory to switch off the DC/DC Converter before entering in Power-down mode.
The DC/DC Converter can work in two different modes which are selected by bit Mode
in DCCKPS register:
•
•
The DC/DC clock prescaler which is controlled by bits DCCKPS[3:0], in DCCKPS regis-
ter must be configured to set the DC/DC clock to a working frequency of 4 MHz which
depends on the value of the quartz. There is no need to change the default configuration
set by the reset sequence if an 8 MHz quartz is used by the application.
The DC/DC Converter implements a current overflow controller which avoids permanent
damage of the DC/DC converter in case of short circuit between CVCC and CVSS. The
maximum limit is around 100 mA. It is possible to increase this limit in normal operating
Bit Number
XTSCS
5 - 0
The SCIIR register (Table 42 on page 48) controls the CVCC level by means of bits
VCARD[1:0].
The SCCON register (Table 40 on page 46) enables to switch the DC/DC converter
on or off by means of bit CARDVCC.
The DCCKPS register (Table 56 on page 56) controls the DC/DC clock and current.
Pump Mode: an external inductance of 10 µH must be connected between pins LI
and VCC. VCC can be higher or lower than CVCC.
Regulator mode: no external inductance is required but VCC must be always higher
than CVCC.
7
7
6
Mnemonic Description
SCICLK5:0
XTSCS
Bit
6
-
-
Smart Card Clock Selection Bit
If XTSCS bit is set, XTAL1 is SCIB clock.
If XTSCS bit is cleared and EXT48 bit is set , XTAL1 is SCIB clock.
If XTSCS bit is cleared and EXT48 bit is reset, PLL is SCIB clock.
Reserved
The value read from this bit is indeterminate. Do not change these bits.
SCIB clock reload register
Prescaler 2 reload value is used to defines the card clock frequency.
If SCICLK5:0 is smaller than 48
Fck_iso = Fck_pll or Fck_XTAL1/ (2 * (48 - SCICLK5:0))
If SCICLK5:0 is equal to 48
Fck_iso = Fck_XTAL1 or Fck_XTAL1
SCICLK5:0 must be smaller than 49.
SCICLK5
5
SCICLK4
4
SCICLK3
3
SCICLK2
2
SCICLK1
1
4202B–SCR–07/03
SCICLK0
0