AT83EC5123 ATMEL Corporation, AT83EC5123 Datasheet - Page 150

• Manufacturer Part Number: AT83EC5123
• Description: (AT8xx512x) Smart Card Reader ICs
• Manufacturer: ATMEL Corporation

Dual Data Pointer
Register (DDPTR)
Figure 89. Use of Dual Pointer
150
AT8xC5122/23
7
AUXR1(A2H)
DPS
0
•
The stack pointer (SP) may be located anywhere in the 256 bytes RAM (lower and
upper RAM) internal data memory. The stack may not be located in the XRAM.
The M0 bit allows to stretch the XRAM timings; if M0 is set, the read and write pulses
are extended from 6 to 30 clock periods. This is useful to access external slow
peripherals.
The additional data pointer can be used to speed up code execution and reduce code
size.
The dual DPTR structure is a way by which the chip will specify the address of an exter-
nal data memory location. There are two 16-bit DPTR registers that address the external
memory, and a single bit called DPS = AUXR1.0 (see Table 112) that allow the program
code to switch between them (Figure 89).
a. Bit 2 stuck at 0; this allows to use INC AUXR1 to toggle DPS without changing GF3.
With EXTRAM = 1, MOVX @Ri and MOVX @DPTR will be similar to the standard
80C51. MOVX @ Ri will provide an eight-bit address multiplexed with data on Port 0
and any output port pins can be used to output higher order address bits. This is to
provide the external paging capability. MOVX @DPTR will generate a sixteen-bit
address. Port 2 outputs the high-order eight address bits (the contents of DPH)
while Port0 multiplexes the low-order eight address bits (DPL) with data. MOVX @
Ri and MOVX @DPTR will generate either read or write signals on P3.6 (WR) and
P3.7 (RD).
DPH(83H) DPL(82H)
DPTR1
DPTR0
External Data Memory
4202B–SCR–07/03