AT83EC5123 ATMEL Corporation, AT83EC5123 Datasheet - Page 79

• Manufacturer Part Number: AT83EC5123
• Description: (AT8xx512x) Smart Card Reader ICs
• Manufacturer: ATMEL Corporation

4202B–SCR–07/03
Table 60. USB Global Interrupt Register - USBINT (S:BDh)
Reset Value = 0000 0000b
Bit Number
7 - 6
2-1
7
5
4
3
0
-
Mnemonic Description
WUPCPU
EORINT
SOFINT
SPINT
Bit
6
-
-
-
Reserved
The value read from these bits is always 0. Do not change these bits.
Wake-up CPU Interrupt
This bit is set by hardware when the USB controller is in SUSPEND state and is
re-activated by a non-idle signal FROM USB line (not by an upstream resume).
This triggers a USB interrupt when EWUPCPU is set in the Table on page 80.
When receiving this interrupt, user has to enable all USB clock inputs.
This bit should be cleared by software (USB clocks must be enabled before).
End of Reset Interrupt
This bit is set by hardware when a End of Reset has been detected by the USB
controller. This triggers a USB interrupt when EEORINT is set in the Table on
page 80.
This bit should be cleared by software.
Start Of Frame Interrupt
This bit is set by hardware when an USB Start Of Frame PID (SOF) has been
detected. This triggers a USB interrupt when ESOFINT is set in the Table on
page 80.
This bit should be cleared by software.
Reserved
The value read from these bits is always 0. Do not change these bits.
Suspend Interrupt
This bit is set by hardware when a USB Suspend (Idle bus for three frame
periods: a J state for 3 ms) is detected. This triggers a USB interrupt when
ESPINT is set in the Table on page 80.
This bit should be cleared by software BEFORE any other USB operation to re-
activate the macro.
WUPCPU
5
EORINT
4
SOFINT
3
2
AT8xC5122/23
-
1
-
SPINT
0
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