F25L04UA-100PG ESMT [Elite Semiconductor Memory Technology Inc.], F25L04UA-100PG Datasheet - Page 7

• Manufacturer Part Number: F25L04UA-100PG
• Description: 3V Only 4 Mbit Serial Flash Memory
• Manufacturer: ESMT [Elite Semiconductor Memory Technology Inc.]

ESMT
Instructions
Instructions are used to Read, Write (Erase and Program), and
configure the F25L04UA. The instruction bus cycles are 8 bits
each for commands (Op Code), data, and addresses. Prior to
executing any Byte-Program, Auto Address Increment (AAI)
programming,
instructions, the Write-Enable (WREN) instruction must be
executed first. The complete list of the instructions is provided in
Table 5. All instructions are synchronized off a high to low
transition of CE . Inputs will be accepted on the rising edge of
TABLE 5: DEVICE OPERATION INSTRUCTIONS
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. The Jedec-Read-ID is output first byte 8CH as manufacture ID; second byte 8CH as top memory type; third byte 8CH as memory
11. The Write-Enable (WREN) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction of each other.
Elite Semiconductor Memory Technology Inc.
Read
High-Speed-Read
Sector-Erase
Chip-Erase
Byte-Program
Auto Address Increment -
word programming (AAI)
Read-Status-Register
(RDSR)
Enable-Write-Status-Register
(EWSR)
Write-Status-Register
(WRSR)
Write-Enable (WREN)
Write-Disable (WRDI)
Jedec-Read-ID (JEDEC-ID)
Operation: S
X = Dummy Input Cycles (V
One bus cycle is eight clock periods.
Sector addresses: use AMS-A12, remaining addresses can be V
Prior to any Byte-Program, AAI-Program, Sector-Erase ,or Chip-Erase operation, the Write-Enable (WREN) instruction must be
executed.
To continue programming to the next sequential address location, enter the 8-bit command, AFH, followed by the data to be
programmed.
The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE .
The Enable-Write-Status-Register (EWSR) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction
of each other. The WRSR instruction must be executed immediately (very next bus cycle) after the EWSR instruction to make both
instructions effective.
The Jedec-Read-ID is continuous with on going clock cycles until terminated by a low to high transition on CE .
capacity.
The WRSR instruction must be executed immediately (very next bus cycle) after the WREN instruction to make both instructions
effective. Both EWSR and WREN can enable WRSR, user just need to execute one of it. A successful WRSR can reset WREN.
Operation
8
8
Cycle Type/
5
4,5
5
Sector-Erase,
IN
= Serial In, S
1,2
11
6
10
OUT
IL
Block-Erase,
or V
Freq
Max
MHz
and
and
100
= Serial Out
33
50
75
IH
); - = Non-Applicable Cycles (Cycles are not necessary)
0BH
AFH
03H
20H
60H
02H
05H
50H
01H
06H
04H
9FH
S
IN
1
or
S
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
OUT
Chip-Erase
A
A
A
A
A
Data
23
23
23
23
23
S
X
X
-A
-A
-A
-
-A
-A
-
-
-
IN
16
16
16
16
16
2
D
S
8CH
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
IL
OUT
OUT
-
-
-
SCK starting with the most significant bit. CE must be driven
low before an instruction is entered and must be driven high after
the last bit of the instruction has been shifted in (except for Read,
Read-ID and Read-Status-Register instructions). Any low to high
transition on CE , before receiving the last bit of an instruction
bus cycle, will terminate the instruction in progress and return the
device to the standby mode.
Instruction commands (Op Code), addresses, and data are all
input from the most significant bit (MSB) first.
or V
IH
A
A
A
A
A
15
15
15
15
15
S
X
-
-
-
-
-
IN
-A
-A
-A
-A
-A
8
8
8
8
8
3
Bus Cycle4
Note
S
8CH
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
OUT
-
-
-
-
7
A
A
A
A
A
S
7
7
7
7
7
X
-.
-A
-A
-A
-
-A
-A
-
-
-
IN
Publication Date: Jan. 2009
Revision:
0
0
0
0
0
4
Note
S
8CH
Hi-Z
Hi-Z
Hi-Z
Hi-Z D
Hi-Z D
OUT
F25L04UA
-
-
-
-
7
S
X
X
-
-
-
-
-
-
-
IN
IN
IN
1.2
5
Note
D
S
Hi-Z
Hi-Z
OUT
OUT
X
-
-
-
-
-
-
7
7/25
S
X
IN
6
S
D
OUT
OUT