F25L04UA-100PG ESMT [Elite Semiconductor Memory Technology Inc.], F25L04UA-100PG Datasheet - Page 14

• Manufacturer Part Number: F25L04UA-100PG
• Description: 3V Only 4 Mbit Serial Flash Memory
• Manufacturer: ESMT [Elite Semiconductor Memory Technology Inc.]

ESMT
Write-Enable (WREN)
The Write-Enable (WREN) instruction sets the Write-
Enable-Latch bit to 1 allowing Write operations to occur.
The WREN instruction must be executed prior to any Write
(Program/Erase) operation. CE must be driven high before the
WREN instruction is executed.
Write-Disable (WRDI)
The Write-Disable (WRDI) instruction resets the Write-Enable-Latch
bit and AAI bit to 0 disabling any new Write operations from occurring.
Figure 12 : WRITE DISABLE (WRDI) SEQUENCE
Enable-Write-Status-Register (EWSR)
The Enable-Write-Status-Register (EWSR) instruction arms the
Write-Status-Register (WRSR) instruction and opens the status
register
instruction does not have any effect and will be wasted, if it is not
followed immediately by the Write-Status-Register (WRSR)
instruction. CE must be driven low before the EWSR instruction
is entered and must be driven high before the EWSR instruction
is executed.
Elite Semiconductor Memory Technology Inc.
CE must be driven high before the WRDI instruction is executed.
FIGURE 11 : WRITE ENABLE (WREN) SEQUENCE
for
alteration.
The
Enable-Write-Status-Register
SCK
SO
CE
SI
SCK
MODE0
MODE3
SO
CE
SI
MODE0
MODE3
MSB
HIGH IMPENANCE
0 1 2 3 4 5 6 7
MSB
HIGH IMPENANCE
0 1 2 3 4 5 6 7
06
04
Publication Date: Jan. 2009
Revision:
F25L04UA
1.2
14/25