A3P015-1FG144 ACTEL [Actel Corporation], A3P015-1FG144 Datasheet - Page 87

• Manufacturer Part Number: A3P015-1FG144
• Description: ProASIC3 Flash Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

Figure 2-22 • Output DDR Timing Diagram
Table 2-95 • Output DDR Propagation Delays
Data_F
Data_R
CLK
CLR
Out
Parameter
t
t
t
t
t
t
t
t
t
t
t
F
Note:
DDROCLKQ
DDROSUD1
DDROSUD2
DDROHD1
DDROHD2
DDROCLR2Q
DDROREMCLR
DDRORECCLR
DDROWCLR1
DDROCKMPWH
DDROCKMPWL
DDOMAX
For specific junction temperature and voltage supply levels, refer to
values.
6
t
Timing Characteristics
DDROCLR2Q
Commercial-Case Conditions: T
1
Clock-to-Out of DDR for Output DDR
Data_F Data Setup for Output DDR
Data_R Data Setup for Output DDR
Data_F Data Hold for Output DDR
Data_R Data Hold for Output DDR
Asynchronous Clear-to-Out for Output DDR
Asynchronous Clear Removal Time for Output DDR
Asynchronous Clear Recovery Time for Output DDR
Asynchronous Clear Minimum Pulse Width for Output DDR
Clock Minimum Pulse Width HIGH for the Output DDR
Clock Minimum Pulse Width LOW for the Output DDR
Maximum Frequency for the Output DDR
t
DDROREMCLR
t
DDROREMCLR
7
2
t
t
DDROCLKQ
DDROHD1
7
Description
t
J
DDROSUD2
= 70°C, Worst-Case V
8
3
2
v1.3
t
DDROHD2
8
CC
= 1.425 V
4
9
3
ProASIC3 DC and Switching Characteristics
Table 2-6 on page 2-6
0.70 0.80 0.94 1.13
0.38 0.43 0.51 0.61
0.38 0.43 0.51 0.61
0.00 0.00 0.00 0.00
0.00 0.00 0.00 0.00
0.80 0.91 1.07 1.29
0.00 0.00 0.00 0.00
0.22 0.25 0.30 0.36
0.22 0.25 0.30 0.36
0.36 0.41 0.48 0.57
0.32 0.37 0.43 0.52
TBD TBD TBD TBD
–2
t
DDRORECCLR
9
–1
10
4
Std.
5
for derating
–F
10
Units
MHz
11
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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