A3P015-1FG144 ACTEL [Actel Corporation], A3P015-1FG144 Datasheet - Page 85

• Manufacturer Part Number: A3P015-1FG144
• Description: ProASIC3 Flash Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

Out_QR
Figure 2-20 • Input DDR Timing Diagram
Table 2-93 • Input DDR Propagation Delays
Out_QF
Parameter
t
t
t
t
t
t
t
t
t
t
t
F
Note:
DDRICLKQ1
DDRICLKQ2
DDRISUD
DDRIHD
DDRICLR2Q1
DDRICLR2Q2
DDRIREMCLR
DDRIRECCLR
DDRIWCLR
DDRICKMPWH
DDRICKMPWL
DDRIMAX
Data
CLK
CLR
For specific junction temperature and voltage-supply levels, refer to
values.
Timing Characteristics
Commercial-Case Conditions: T
Clock-to-Out Out_QR for Input DDR
Clock-to-Out Out_QF for Input DDR
Data Setup for Input DDR (Fall)
Data Setup for Input DDR (Rise)
Data Hold for Input DDR (Fall)
Data Hold for Input DDR (Rise)
Asynchronous Clear-to-Out Out_QR for Input DDR
Asynchronous Clear-to-Out Out_QF for Input DDR
Asynchronous Clear Removal time for Input DDR
Asynchronous Clear Recovery time for Input DDR
Asynchronous Clear Minimum Pulse Width for Input DDR
Clock Minimum Pulse Width High for Input DDR
Clock Minimum Pulse Width Low for Input DDR
Maximum Frequency for Input DDR
t
t
1
DDRICLR2Q1
DDRICLR2Q2
t
DDRIREMCLR
2
3
Description
t
DDRICLKQ1
J
= 70°C, Worst Case V
4
2
v1.3
3
5
CC
t
DDRICLKQ2
t
= 1.425 V
DDRISUD
6
ProASIC3 DC and Switching Characteristics
4
Table 2-6 on page 2-6
0.32
0.27
0.39
0.25
0.25
0.00
0.00
0.46
0.57
0.00
0.22
0.22
0.36
5
–2
7
0.31
0.44
0.28
0.28
0.00
0.00
0.53
0.65
0.00
0.25
0.25
0.41
0.37
–1
t
DDRIHD
0.37
0.52
0.33
0.33
0.00
0.00
0.62
0.76
0.00
0.30
0.30
0.48
0.43
Std.
t
8
DDRIRECCLR
6
7
0.44
0.62
0.40
0.40
0.00
0.00
0.74
0.92
0.00
0.36
0.36
0.57
0.52
for derating
–F
9
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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