A3P015-1FG144 ACTEL [Actel Corporation], A3P015-1FG144 Datasheet - Page 74

• Manufacturer Part Number: A3P015-1FG144
• Description: ProASIC3 Flash Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

ProASIC3 DC and Switching Characteristics
Figure 2-12 • B-LVDS/M-LVDS Multipoint Application Using LVDS I/O Buffers
2 -6 0
R
T
Z
Z
Z
0
0
stub
Receiver
+
R
R
S
B-LVDS/M-LVDS
Bus LVDS (B-LVDS) and Multipoint LVDS (M-LVDS) specifications extend the existing LVDS standard
to high-performance multipoint bus applications. Multidrop and multipoint bus configurations
may contain any combination of drivers, receivers, and transceivers. Actel LVDS drivers provide the
higher drive current required by B-LVDS and M-LVDS to accommodate the loading. The drivers
require series terminations for better signal quality and to control voltage swing. Termination is
also required at both ends of the bus since the driver can be located anywhere on the bus. These
configurations can be implemented using the TRIBUF_LVDS and BIBUF_LVDS macros along with
appropriate terminations. Multipoint designs using Actel LVDS macros can achieve up to 200 MHz
with a maximum of 20 loads. A sample application is given in
buffer delays are available in the LVDS section in
Example: For a bus consisting of 20 equidistant loads, the following terminations provide the
required differential voltage, in worst-case Industrial operating conditions, at the farthest receiver:
R
-
S
EN
R
Z
= 60
S
stub
and R
Z
Z
Z
0
0
stub
Transceiver
+
T
R
T
= 70 , given Z
S
-
EN
R
Z
S
stub
Z
Z
Z
0
0
stub
0
Driver
+
= 50
R
D
S
-
EN
R
Z
S
stub
(2") and Z
v1.3
Z
Z
Z
0
0
stub
Table
Receiver
stub
+
R
R
S
= 50
-
2-83.
EN
R
Z
S
stub
(~1.5").
...
Figure
Z
Z
2-12. The input and output
0
0
Transceiver
+
R
T
S
-
EN
R
S
BIBUF_LVDS
Z
Z
0
0
R
T