A3P015-1FG144 ACTEL [Actel Corporation], A3P015-1FG144 Datasheet - Page 120

• Manufacturer Part Number: A3P015-1FG144
• Description: ProASIC3 Flash Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

ProASIC3 DC and Switching Characteristics
2 -1 0 6
Previous Version
Advance v0.7
(continued)
Advance v0.5
(January 2006)
In EQ 3-2, 150 was changed to 110 and the result changed from 3.9 to 1.951.
Table 3-6 • Temperature and Voltage Derating Factors for Timing Delays was
updated.
Table 3-5 • Package Thermal Resistivities was updated.
Table 3-14 • Summary of Maximum and Minimum DC Input and Output Levels
Applicable to Commercial and Industrial Conditions—Software Default Settings
(Advanced) and Table 3-17 • Summary of Maximum and Minimum DC Input
Levels Applicable to Commercial and Industrial Conditions (Standard Plus) were
updated.
Table 3-20 • Summary of I/O Timing Characteristics—Software Default Settings
(Advanced) and Table 3-21 • Summary of I/O Timing Characteristics—Software
Default Settings (Standard Plus) were updated.
Table
Consumption in ProASIC3 Devices was updated.
Table 3-24 • I/O Output Buffer Maximum Resistances1 (Advanced) and Table 3-
25 • I/O Output Buffer Maximum Resistances1 (Standard Plus) were updated.
Table 3-17 • Summary of Maximum and Minimum DC Input Levels Applicable to
Commercial and Industrial Conditions was updated.
Table 3-28 • I/O Short Currents IOSH/IOSL (Advanced) and Table 3-29 • I/O
Short Currents IOSH/IOSL (Standard Plus) were updated.
The note in Table 3-32 • I/O Input Rise Time, Fall Time, and Related I/O
Reliability was updated.
Figure 3-33 • Write Access After Write onto Same Address, Figure 3-34 • Read
Access After Write onto Same Address, and Figure 3-35 • Write Access After
Read onto Same Address are new.
Figure 3-43 • Timing Diagram was updated.
B-LVDS and M-LDVS are new I/O standards added to the datasheet.
The term flow-through was changed to pass-through.
Figure 2-7 • Efficient Long-Line Resources was updated.
The footnotes in Figure 2-15 • Clock Input Sources Including CLKBUF,
CLKBUF_LVDS/LVPECL, and CLKINT were updated.
The Delay Increments in the Programmable Delay Blocks specification in Figure
2-24 • ProASIC3E CCC Options.
The "SRAM and FIFO" section was updated.
The "RESET" section was updated.
The "WCLK and RCLK" section was updated.
The "RESET" section was updated.
The "RESET" section was updated.
The "Introduction" of the "Advanced I/Os" section was updated.
3-11 • Different
Changes in Current Version (v1.3)
Components
v1.3
Contributing
to
Dynamic
Power
3-17 to
3-20 to
3-22 to
3-24 to
3-82 to
Page
3-17
3-20
3-22
3-18
3-26
3-27
3-84
3-96
2-16
2-24
2-21
2-25
2-25
2-25
2-27
2-28
N/A
N/A
3-5
3-6
3-5
3-9
2-7