A3P015-1FG144 ACTEL [Actel Corporation], A3P015-1FG144 Datasheet - Page 119

• Manufacturer Part Number: A3P015-1FG144
• Description: ProASIC3 Flash Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

Previous Version
v1.0
(continued)
v2.2
(July 2007)
v2.1
(May 2007)
v2.0
(April 2007)
Advance v0.7
(January 2007)
In
are new.
in the previous version of the document.
This document was previously in datasheet v2.2. As a result of moving to the
handbook format, Actel restarted the version numbers so the new version
number is v1.0.
The T
changed to T
Table 3-5 • Package Thermal Resistivities was updated with A3P1000
information. The note below the table is also new.
The timing characteristics tables were updated.
The "PLL Macro" section was updated to add information on the VCO and PLL
outputs during power-up.
The "PLL Macro" section was updated to include power-up information.
Table 2-11 • ProASIC3 CCC/PLL Specification was updated.
Figure 2-19 • Peak-to-Peak Jitter Definition is new.
The "SRAM and FIFO" section was updated with operation and timing
requirement information.
The "RESET" section was updated with read and write information.
The "RESET" section was updated with read and write information.
The "Introduction" in the "Advanced I/Os" section was updated to include
information on input and output buffers being disabled.
PCI-X 3.3 V was added to Table 2-11 • VCCI Voltages and Compatible Standards.
In the Table 2-15 • Levels of Hot-Swap Support, the ProASIC3 compliance
descriptions were updated for levels 3 and 4.
Table 2-43 • I/O Hot-Swap and 5 V Input Tolerance Capabilities in ProASIC3
Devices was updated.
Notes 3, 4, and 5 were added to Table 2-17 • Comparison Table for 5 V–
Compliant Receiver Scheme. 5 x 52.72 was changed to 52.7 and the Maximum
current was updated from 4 x 52.7 to 5 x 52.7.
The "VCCPLF PLL Supply Voltage" section was updated.
The "VPUMP Programming Supply Voltage" section was updated.
The "GL Globals" section was updated to include information about direct input
into quadrant clocks.
V
In Table 2-22 • Recommended Tie-Off Values for the TCK and TRST Pins, TSK
was changed to TCK in note 2. Note 3 was also updated.
Ambient was deleted from Table 3-2 • Recommended Operating Conditions.
VPUMP programming mode was changed from "3.0 to 3.6" to "3.15 to 3.45".
Note 3 is new in Table 3-4 • Overshoot and Undershoot Limits (as measured on
quiet I/Os)1.
Table 2-116 · JTAG 1532
JTAG
Table 2-106 · ProASIC3 CCC/PLL
was deleted from the "TCK Test Clock" section.
J
parameter in Table 3-2 • Recommended Operating Conditions was
A
, ambient temperature, and table notes 4–6 were added.
Changes in Current Version (v1.3)
was populated with the parameter data, which was not
v1.3
Specification, the SCLK parameter and note 1
ProASIC3 DC and Switching Characteristics
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