WM8951L_07 WOLFSON [Wolfson Microelectronics plc], WM8951L_07 Datasheet - Page 22

• Manufacturer Part Number: WM8951L_07
• Description: Stereo ADC with Microphone Input and Clock Generator
• Manufacturer: WOLFSON [Wolfson Microelectronics plc]

WM8951L
Figure 17 Left Justified Mode
Figure 18 I
w
2
S Mode
The digital audio interface takes the data from the internal ADC digital filter and places it on the
ADCDAT output. ADCDAT is the formatted digital audio data stream output from the ADC digital
filters with left and right channels multiplexed together. ADCLRC is an alignment clock that controls
whether Left or Right channel data is present on the ADCDAT lines. ADCDAT and ADCLRC are
synchronous with the BCLK signal with each data bit transition signified by a BCLK high to low
transition. BCLK maybe an input or an output dependent on whether the device is in master or slave
mode. Refer to the MASTER/SLAVE OPERATION section
There are four digital audio interface formats accommodated by the WM8951L. These are shown in
the figures below. Refer to the Electrical Characteristic section for timing information.
Left Justified mode is where the MSB is available on the first rising edge of BCLK following a ADCLR
transition.
I
transition.
Right Justified mode is where the LSB is available on the rising edge of BCLK preceding a ADCLRC
transition, yet MSB is still transmitted first.
2
S mode is where the MSB is available on the 2nd rising edge of BCLK following an ADCLRC
PD Rev 4.1 December 2007
Production Data
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