WM8951L_07 WOLFSON [Wolfson Microelectronics plc], WM8951L_07 Datasheet - Page 21

• Manufacturer Part Number: WM8951L_07
• Description: Stereo ADC with Microphone Input and Clock Generator
• Manufacturer: WOLFSON [Wolfson Microelectronics plc]

Production Data
w
Figure 16 Crystal Oscillator Application Circuit
The WM8951L crystal oscillator provides an extremely low jitter clock source. Low jitter clocks are a
requirement for high quality audio ADCs, regardless of the converter architecture. The WM8951L
architecture is less susceptible than most converter techniques but still requires clocks with less than
approximately 1ns of jitter to maintain performance. In applications where there is more than one
source for the master clock, it is recommended that the clock is generated by the WM8951L to
minimise such problems.
CLOCKOUT
The Core Clock is internally buffered and made available externally to the audio system on the
CLKOUT output pin. CLKOUT provides a replication of the Core Clock, but buffered as suitable for
driving external loads.
There is no phase inversion between XTI/MCLK, the Core Clock and CLOCKOUT but there will
inevitably be some delay. The delay will be dependent on the load that CLOCKOUT drives. Refer to
Electrical Characteristics.
CLKOUT can also be divided by 2 under software control, refer to Table 8. Note that if CLKOUT is
not required then the CLKOUT buffer on the WM8951L can be safely powered down to conserve
power (see POWER DOWN section). If the system architect has the choice between using F
F
divide by two is selected CLKOUT changes on the rising edge of MCLK. Please refer to Electrical
Characteristics for timing information.
Table 8 Programming CLKOUT
CLKOUT is disabled and set low whenever the device is in reset.
DIGITAL AUDIO INTERFACES
WM8951L may be operated in either one of the 4 offered audio interface modes. These are:
•
•
•
•
All four of these modes are MSB first and operate with data 16 to 32 bits.
Note that 32 bit data is not supported in right justified mode.
MCLK
0001000
Sampling
Control
REGISTER
ADDRESS
Right justified
Left justified
I
DSP mode
2
S
or F
Cp
XTI/MCLK
CLKOUT
DGND
= F
7
BIT
MCLK
/2 in the interface, the latter is recommended to conserve power. When the
CLKODIV2
LABEL
DGND
XTO
Cp
0
DEFAULT
CLKOUT divider select
1 = CLOCKOUT is Core Clock
divided by 2
0 = CLOCKOUT is Core Clock
DESCRIPTION
PD Rev 4.1 December 2007
WM8951
CLKOUT
21
=