WM8951L_07 WOLFSON [Wolfson Microelectronics plc], WM8951L_07 Datasheet - Page 20

• Manufacturer Part Number: WM8951L_07
• Description: Stereo ADC with Microphone Input and Clock Generator
• Manufacturer: WOLFSON [Wolfson Microelectronics plc]

WM8951L
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DEVICE OPERATION
DEVICE RESETTING
The WM8951L contains a power on reset circuit that resets the internal state of the device to a
known condition. The power on reset is applied as DCVDD powers on and released only after the
voltage level of DCVDD crosses a minimum turn off threshold. If DCVDD later falls below a minimum
turn on threshold voltage then the power on reset is re-applied. The threshold voltages and
associated hysteresis are shown in the Electrical Characteristics table.
The user also has the ability to reset the device to a known state under software control as shown in
the table below.
Table 6 Software Control of Reset
When using the software reset. In 3-wire mode the reset is applied on the rising edge of CSB and
released on the next rising edge of SCLK. In 2-wire mode the reset is applied for the duration of the
ACK signal (approximately 1 SCLK period, refer to Figure 24).
CLOCKING SCHEMES
In a typical digital audio system there is only one central clock source producing a reference clock to
which all audio data processing is synchronised. This clock is often referred to as the audio system’s
Master Clock. To allow WM8951L to be used in a centrally clocked system, the WM8951L is capable
of either generating this system clock itself or receiving it from an external source as will be
discussed.
For applications where it is desirable that the WM8951L is the system clock source, then clock
generation is achieved through the use of a suitable crystal connected between the XTI/MCLK input
and XTO output pins (see CRYSTAL OSCILLATOR section).
For applications where a component other than the WM8951L will generate the reference clock, the
external system can be applied directly through the XTI/MCLK input pin with no software
configuration necessary. Note that in this situation, the oscillator circuit of the WM8951L can be
safely powered down to conserve power (see POWER DOWN section).
CORE CLOCK
The WM8951L DSP core can be clocked either by MCLK or MCLK divided by 2. This is controlled by
software as shown in Table 7 below.
Table 7 Software Control of Core Clock
Having a programmable MCLK divider allows the device to be used in applications where higher
frequency master Clocks are available. For example the device can support 512fs master clocks
whilst fundamentally operating in a 256fs mode.
CRYSTAL OSCILLATOR
The WM8951L includes a crystal oscillator circuit that allows the audio system’s reference clock to
be generated on the device. This is available to the rest of the audio system in buffered form on
CLKOUT. The crystal oscillator is a low radiation type, designed for low EMI. A typical application
circuit is shown in Figure 16.
0001111
Reset Register
0001000
Sampling
Control
REGISTER
ADDRESS
REGISTER
ADDRESS
6
BIT
8:0
BIT
CLKIDIV2
RESET
LABEL
LABEL
0
DEFAULT
not reset
DEFAULT
Reset Register
Writing 00000000 to register resets
device
1 = Core Clock is MCLK divided by 2
0 = Core Clock is MCLK
Core Clock divider select
DESCRIPTION
DESCRIPTION
PD Rev 4.1 December 2007
Production Data
20