XR16C854CV EXAR [Exar Corporation], XR16C854CV Datasheet - Page 6

• Manufacturer Part Number: XR16C854CV
• Description: 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
• Manufacturer: EXAR [Exar Corporation]

Pin Description
XR16C854/854D
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
MODEM OR SERIAL I/O INTERFACE
RXRDY#
TXRDY#
DTRC#
DTRD#
DSRA#
DSRB#
DSRC#
DSRD#
FSRS#
RTSA#
RTSB#
RTSC#
RTSD#
CTSA#
CTSB#
CTSC#
CTSD#
DTRA#
DTRB#
IRTXA
IRTXB
IRTXC
IRTXD
N
RXC
RXD
TXC
TXD
RXA
RXB
TXA
TXB
AME
64-LQFP
P
10
39
41
62
20
29
51
13
36
44
16
33
47
15
34
46
17
32
48
IN
8
5
2
3
1
-
-
-
-
-
-
-
#
68-PLCC
P
39
38
17
19
51
53
29
41
63
14
22
48
56
25
45
59
12
24
46
58
10
26
44
60
11
IN
7
-
-
-
-
-
#
100-QFP
P
45
44
76
14
16
65
67
24
57
75
97
34
47
85
11
19
62
70
22
59
73
21
60
72
23
58
74
IN
6
8
9
7
#
T
YPE
O
O
O
O
O
O
I
I
I
I
Transmitter Ready (active low). This output is a logically wire-
ORed status of TXRDY# A-D. See
unused, leave it unconnected.
Receiver Ready (active low). This output is a logically wire-ORed
status of RXRDY# A-D. See
leave it unconnected.
FIFO Status Register Select (active low input with internal pull-up).
The content of the FSTAT register is placed on the data bus when
this pin becomes active. However it should be noted, D0-D3 con-
tain the inverted logic states of TXRDY# A-D pins, and D4-D7 the
logic states (un-inverted) of RXRDY# A-D pins. Address line is not
required when reading this status register.
UART channels A-D Transmit Data and infrared transmit data.
Standard transmit and receive interface is enabled when MCR[6] =
0. In this mode, the TX signal will be a logic 1 during reset, or idle
(no data). Infrared IrDA transmit and receive interface is enabled
when MCR[6] = 1. In the Infrared mode, the inactive state (no
data) for the Infrared encoder/decoder interface is a logic 0.
UART channel A-D Infrared Transmit Data. The inactive state (no
data) for the Infrared encoder/decoder interface is a logic 0.
Regardless of the logic state of MCR bit-6, this pin will be operating
in the Infrared mode.
UART channel A-D Receive Data or infrared receive data. Normal
receive data input must idle at logic 1 condition. The infrared
receiver pulses typically idles at logic 0 but can be inverted by soft-
ware control prior going in to the decoder, see FCTR[2].
UART channels A-D Request-to-Send (active low) or general pur-
pose output. This output must be asserted prior to using auto RTS
flow control, see EFR[6], MCR[1], FCTR[1:0], EMSR[5:4] and
IER[6]. Also see
them unconnected.
UART channels A-D Clear-to-Send (active low) or general purpose
input. It can be used for auto CTS flow control, see EFR[7], and
IER[7]. Also see
to VCC when not used.
UART channels A-D Data-Terminal-Ready (active low) or general
purpose output. If these outputs are not used, leave them uncon-
nected.
UART channels A-D Data-Set-Ready (active low) or general pur-
pose input. This input should be connected to VCC when not used.
6
Figure 11
Figure 11
D
ESCRIPTION
. If these outputs are not used, leave
. These inputs should be connected
Table
5. If this output is unused,
Table
5. If this output is
xr
REV. 3.0.1