XR16C854CV EXAR [Exar Corporation], XR16C854CV Datasheet - Page 21

• Manufacturer Part Number: XR16C854CV
• Description: 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
• Manufacturer: EXAR [Exar Corporation]

xr
REV. 3.0.1
The 854 resumes normal operation by any of the following:
If the 854 is awakened by any one of the above conditions, it will return to the sleep mode automatically after
all interrupting conditions have been serviced and cleared. If the 854 is awakened by the modem inputs, a read
to the MSR is required to reset the modem inputs. In any case, the sleep mode will not be entered while an
interrupt is pending in any channel. The 854 will stay in the sleep mode of operation until it is disabled by
setting IER bit-4 to a logic 0.
If the address lines, data bus lines, IOW#, IOR#, CSA#, CSB#, CSC#, CSD# and modem input lines remain
steady when the 854 is in sleep mode, the maximum current will be in the microamp range as specified in the
DC Electrical Characteristics on
mode, the current can be up to 100 times more. If any of those signals are toggling or floating, then an external
buffer would be required to keep the address, data and control lines steady to achieve the low current.
A word of caution: owing to the starting up delay of the crystal oscillator after waking up from sleep mode, the
first few receive characters may be lost. Also, make sure the RX input is idling at logic 1 or “marking” condition
during sleep mode. This may not occur when the external interface transceivers (RS-232, RS-485 or another
type) are also put to sleep mode and cannot maintain the “marking” condition. To avoid this, the system design
engineer can use a 47k ohm pull-up resistor on the RX A-D inputs.
The 854 UART provides an internal loopback capability for system diagnostic purposes. The internal loopback
mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally.
Figure 13
output is internally routed to the receive shift register input allowing the system to receive the same data that it
was sending. The TX pin is held at logic 1 or mark condition while RTS# and DTR# are de-asserted, and
CTS#, DSR# CD# and RI# inputs are ignored. Caution: the RX input must be held to a logic 1 during loopback
test else upon exiting the loopback test the UART may detect and report a false “break” signal.
2.20
■
■
■
a receive data start bit transition (logic 1 to 0)
a data byte is loaded to the transmitter, THR or FIFO
a change of logic state on any of the modem or general purpose serial inputs: CTS#, DSR#, CD#, RI#
Internal Loopback
shows how the modem port signals are re-configured. Transmit data from the transmit shift register
page
41. If the input lines are floating or are toggling while the 854 is in sleep
21
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
XR16C854/854D