XR16C854CV EXAR [Exar Corporation], XR16C854CV Datasheet - Page 36

• Manufacturer Part Number: XR16C854CV
• Description: 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
• Manufacturer: EXAR [Exar Corporation]

XR16C854/854D
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
EMSR[5:4]: Extended RTS Hysteresis
EMSR[7:6]: Reserved
The FIFO Level Register replaces the Scratchpad Register (during a Read) when FCTR[6] = 1. Note that this
is not identical to the FIFO Data Count Register which can be accessed when LCR = 0xBF.
FLVL[7:0]: FIFO Level Register
This register provides the FIFO counter level for the RX FIFO or the TX FIFO or both depending on EMSR[1:0].
See Table 14
The concatenation of the contents of DLM and DLL gives the 16-bit divisor value which is used to calculate the
baud rate:
•
See MCR bit-7 and the baud rate table also.
This register contains the device ID (0x14 for XR16C854). Prior to reading this register, DLL and DLM should
be set to 0x00.
This register contains the device revision information. For example, 0x01 means revision A. Prior to reading
this register, DLL and DLM should be set to 0x00.
User Programmable Transmit/Receive Trigger Level Register.
TRG[7:0]: Trigger Level Register
These bits are used to program desired trigger levels when trigger Table-D is selected. FCTR bit-7 selects
between programming the RX Trigger Level (a logic 0) and the TX Trigger Level (a logic 1).
4.12
4.13
4.14
4.15
4.16
Baud Rate = (Clock Frequency / 16) / Divisor
FIFO Level Register (FLVL) - Read-Only
Baud Rate Generator Registers (DLL and DLM) - Read/Write
Device Identification Register (DVID) - Read Only
Device Revision Register (DREV) - Read Only
Trigger Level (TRG) - Write-Only
for details.
EMSR
B
IT
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
-5
T
ABLE
EMSR
B
IT
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
-4
15: A
FCTR
B
UTO
IT
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
-1
36
RTS H
FCTR
B
IT
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
YSTERESIS
-0
(C
H
HARACTERS
YSTERESIS
RTS#
±16
±24
±32
±40
±44
±48
±52
±12
±20
±28
±36
±4
±6
±8
±8
0
)
xr
REV. 3.0.1