XR16C854CV EXAR [Exar Corporation], XR16C854CV Datasheet - Page 54

• Manufacturer Part Number: XR16C854CV
• Description: 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
• Manufacturer: EXAR [Exar Corporation]

XR16C854/854D
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
ELECTRICAL CHARACTERISTICS ................................................................................41
T
ABLE OF
A
T
DC E
AC E
TA=0
P
R
YPICAL
4.4 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY ............................................................................... 27
4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY ...................................................................................... 28
4.6 LINE CONTROL REGISTER (LCR) - READ/WRITE ...................................................................................... 30
4.7 MODEM CONTROL REGISTER (MCR) OR GENERAL PURPOSE OUTPUTS CONTROL - READ/WRITE 32
4.8 LINE STATUS REGISTER (LSR) - READ ONLY ........................................................................................... 33
4.9 MODEM STATUS REGISTER (MSR) - READ ONLY .................................................................................... 34
4.10 SCRATCH PAD REGISTER (SPR) - READ/WRITE .................................................................................... 35
4.11 ENHANCED MODE SELECT REGISTER (EMSR) ...................................................................................... 35
4.12 FIFO LEVEL REGISTER (FLVL) - READ-ONLY .......................................................................................... 36
4.13 BAUD RATE GENERATOR REGISTERS (DLL AND DLM) - READ/WRITE .............................................. 36
4.14 DEVICE IDENTIFICATION REGISTER (DVID) - READ ONLY .................................................................... 36
4.15 DEVICE REVISION REGISTER (DREV) - READ ONLY .............................................................................. 36
4.16 TRIGGER LEVEL (TRG) - WRITE-ONLY ..................................................................................................... 36
4.17 FIFO DATA COUNT REGISTER (FC) - READ-ONLY .................................................................................. 37
4.18
4.19 ENHANCED FEATURE REGISTER (EFR) - READ/WRITE ........................................................................ 37
4.20 SOFTWARE FLOW CONTROL REGISTERS (XOFF1, XOFF2, XON1, XON2) - READ/WRITE ................ 39
4.21 FIFO STATUS REGISTER (FSTAT) - READ/WRITE ................................................................................... 39
BSOLUTE
TA=0o to 70oC (-40o to +85oC for industrial grade package), Vcc is 2.97 to 5.5V.................................................. 41
ACKAGE
EVISION
T
T
T
T
T
T
T
T
T
F
F
F
F
F
F
F
F
F
F
F
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
IGURE
IGURE
IGURE
IGURE
IGURE
IGURE
IGURE
IGURE
IGURE
IGURE
IGURE
LECTRICAL
LECTRICAL
O TO
4.3.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION ................................................................ 26
4.4.1 INTERRUPT GENERATION: ...................................................................................................................................... 27
4.4.2 INTERRUPT CLEARING: ........................................................................................................................................... 27
FEATURE CONTROL REGISTER (FCTR) - READ/WRITE ........................................................................ 37
P
10: I
11: T
12: P
13: INT O
14: S
15: A
16: T
17: S
18: UART RESET CONDITIONS FOR CHANNELS A-D.................................................................................................. 40
14. C
15. M
17. 16 M
16. 16 M
18. 68 M
19. 68 M
20. R
21. T
22. R
23. R
24. T
D
H
C
ACKAGE
M
70
ISTORY
IMENSIONS
ONTENTS
AXIMUM
NTERRUPT
RANSMIT AND
RIGGER
O
ARITY SELECTION
CRATCHPAD
UTO
OFTWARE
RANSMIT
RANSMIT
LOCK
ECEIVE
ECEIVE
ECEIVE
ODEM
C (-40
C
C
RTS H
UTPUT
ODE
ODE
ODE
ODE
HARACTERISTICS
HARACTERISTICS
.......................................................................................................................................52
T
T
T
I
HERMAL
IMING
NPUT
R
R
R
R
ABLE
(I
(I
(M
(M
O TO
S
F
R
R
EADY
EADY
EADY
NTEL
NTEL
.................................................................................................................................49
ATINGS
OURCE AND
LOW
M
YSTERESIS
EADY
EADY
OTOROLA
OTOROLA
S
............................................................................................................
R
ODES
/O
WAP
............................................................................................................................................................. 43
S
ECEIVE
) D
) D
UTPUT
& I
& I
& I
ELECT
C
+85
........................................................................................................................................................ 31
& I
& I
ONTROL
R
S
ATA
ATA
NTERRUPT
NTERRUPT
NTERRUPT
..................................................................................................................................................... 32
......................................................................................................................41
ELECTION
NTERRUPT
NTERRUPT
ESISTANCE
O
) D
) D
................................................................................................................................................ 37
FIFO T
T
............................................................................................................................................... 36
B
B
C
P
IMING
ATA
ATA
US
US
RIORITY
FOR INDUSTRIAL GRADE PACKAGE
F
..............................................................................................................41
..............................................................................................................42
UNCTIONS
W
R
B
B
EAD
T
T
T
RIGGER
.................................................................................................................................... 35
RITE
F
US
US
IMING
T
IMING
IMING
T
OR
IMING
IMING
L
R
W
T
EVEL
D
T
C
EAD
IMING FOR
RITE
IMING FOR
ATA
HANNELS
[N
[FIFO M
[FIFO M
........................................................................................................................ 38
L
[N
[FIFO M
EVEL
T
ON
..................................................................................................................... 28
T
ON
IMING FOR
IMING FOR
(M
-FIFO M
-FIFO M
S
ARGIN OF
ODE
ODE
C
ELECTION
A-D .................................................................................................... 43
C
ODE
HANNELS
HANNELS
II
, DMA D
, DMA E
ODE
, DMA M
C
ODE
C
HANNELS
HANNELS
]
............................................................................................ 29
FOR
]
A-D.................................................................................... 44
FOR
E
A-D .................................................................................. 44
NABLED
ISABLED
RROR
ODE
C
C
A-D........................................................................... 45
HANNELS
A-D ......................................................................... 45
HANNELS
D
]
: = 15%) ..............................................41
]
ISABLED
), V
FOR
FOR
CC IS
C
A-D ............................................................ 46
C
A-D .......................................................... 46
HANNELS
HANNELS
]
FOR
2.97
C
HANNELS
A-D............................................ 47
A-D........................................... 47
TO
5.5V.........................42
A-D............................... 48
xr
REV. 3.0.1
I