TSC80251-SK TEMIC [TEMIC Semiconductors], TSC80251-SK Datasheet - Page 15

• Manufacturer Part Number: TSC80251-SK
• Description: 8/16-bit Microcontroller with Serial Communication Interfaces
• Manufacturer: TEMIC [TEMIC Semiconductors]

UCONFIG1
Configuration Byte 1
Notes:
1. The CSIZE is only available on EPROM/OTPROM products.
2. Two or four bytes are transparently popped according to INTR when using the RETI instruction. INTR must be set if interrupts are used
3. Use only for Step A compatibility; set this bit when WSB1:0# are used.
Note:
1. This selection provides compatibility with the standard 80C51 hardware which has separate external memory spaces for data and code.
Rev. A - May 7, 1999
Bit Number
RD1
with code executing outside region FF:.
1
1
0
0
CSIZE
7
7
6
5
4
3
2
1
0
RD0
0
1
0
1
Bit Mnemonic
TSC87251G2D
TSC80251G2D
TSC83251G2D
I/O pin
I/O pin
I/O pin
P1.7
Table 13. Address Ranges and Usage of RD#, WR# and PSEN# Signals
A17
EMAP#
WSB1#
WSB0#
CSIZE
INTR
WSB
6
-
-
-
-
Read signal for regions 00:
and 01:
On-Chip Code Memory Size bit
Reserved
Reserved
Reserved
Interrupt Mode bit
Wait State B bit
Wait State B bits
On-Chip Code Memory Map bit
P3.7/RD#
I/O pin
A16
A16
Clear to select 16 Kbytes of on-chip code memory (TSC87251G1D product).
Set to select 32 Kbytes of on-chip code memory (TSC87251G2D product).
Set this bit when writing to UCONFIG1.
Set this bit when writing to UCONFIG1.
Set this bit when writing to UCONFIG1.
Clear so that the interrupts push two bytes onto the stack (the two lower bytes of the PC register).
Set so that the interrupts push four bytes onto the stack (the three bytes of the PC register and the
PSW1 register).
Clear to generate one wait state for memory region 01:.
Set for no wait states for memory region 01:.
Select the number of wait states for RD#, WR# and PSEN# signals for external memory accesses
(only region 01:).
Clear to map the upper 16 Kbytes of on-chip code memory (at FF:4000h-FF:7FFFh) to the data
space (at 00:C000h-00:FFFFh).
Set not to map the upper 16 Kbytes of on-chip code memory (at FF:4000h-FF:7FFFh) to the data
space.
5
-
WSB1#
0
0
1
1
Figure 8. Configuration Byte 1
(3)
WSB0#
INTR
(2)
0
1
0
1
Read signal for all external
memory locations
Read signal for all external
memory locations
Read signal for all external
memory locations
Read signal for regions FE:
and FF:
4
Number of Wait States
PSEN#
(1)
WSB
3
3
2
1
0
Description
Write signal for all external
memory locations
Write signal for all external
memory locations
Write signal for all external
memory locations
Write signal for all external
memory locations
WSB1#
TSC80251G2D
2
WR#
WSB0#
1
External Memory
2
256 Kbytes
128 Kbytes
64 Kbytes
64 Kbytes
EMAP#
0
(1)
15