TSC80251-SK TEMIC [TEMIC Semiconductors], TSC80251-SK Datasheet
TSC80251-SK
Related parts for TSC80251-SK
TSC80251-SK Summary of contents
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... Kbyte RAM) and up to 256 Kbytes of external code and data. Additionally, Note: This Datasheet provides the technical description of the TSC80251G2D derivatives. For further information on the device usage, please request the TSC80251 Programmer’s Guide and the TSC80251G1D Design Guide. 2. Typical Applications ...
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... Kbytes to 256 Kbytes TSC87251G2D: 32 Kbytes of On-Chip EPROM/ OTPROM SINGLE PULSE Programming Algorithm TSC83251G2D: 32 Kbytes of On-Chip Masked ROM TSC80251G2D: ROMless Version Four 8-bit Parallel I/O Ports (Ports and 3 of the standard 80C51) Serial I/O Port: full duplex UART (80C51 compatible) with independent Baud Rate Generator ...
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... Memory Address EA#/VPP AWAIT# Bus Interface Unit CPU VDD VSS VSS1 Rev May 7, 1999 P0(AD7-0) RAM 1 Kbyte VSS2 Figure 1. TSC80251G2D Block Diagram TSC80251G2D Timers 0, 1 and 2 UART Baud Rate Generator Event and Waveform Controller 2 I C/SPI/ Wire Controller Watchdog Timer RST ...
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... TSC80251G2D 5. Pin Description 5.1 Pinout P1.4/CEX1/SS# P1.5/CEX2/MISO P1.6/CEX3/SCL/SCK/WAIT# P1.7/A17/CEX4/SDA/MOSI/WCLK P3.7/A16/RD# Figure 2. TSC80251G2D 40-pin DIP package P1.5/CEX2/MISO P1.6/CEX3/SCL/SCK/WAIT# P1.7/A17/CEX4/SDA/MOSI/WCLK P3.0/RXD P3.1/TXD P3.2/INT0# P3.3/INT1# Figure 3. TSC80251G2D 44-pin PLCC Package 4 P1.0/ P1.1/T2EX P1.2/ECI 3 P1.3/CEX0 RST 9 P3.0/RXD 10 TSC80251G2D P3.1/TXD 11 P3.2/INT0# 12 P3.3/INT1# 13 P3.4/T0 14 P3.5/T1 15 P3.6/WR XTAL2 ...
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... P1.5/CEX2/MISO P1.6/CEX3/SCL/SCK/WAIT# P1.7/A17/CEX4/SDA/MOSI/WCLK P3.0/RXD AWAIT# P3.1/TXD P3.2/INT0# P3.3/INT1# P3.4/T0 P3.5/T1 Figure 4. TSC80251G2D 44-pin VQFP Package DIP PLCC VQFP 1 39 VSS1 P1.0/ P1.1/T2EX P1.2/ECI P1.3/CEX0 P1.4/CEX1/SS P1.5/CEX2/MISO P1.6/CEX3/SCL/SCK/WAIT P1.7/A17/CEX4/SDA/MOSI/WCLK RST P3.0/RXD 12 6 AWAIT ...
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... TSC80251G2D 5.2 Signals Signal Type Name th A17 O 18 Address Bit Output to memory as 18th external address bit (A17) in extended bus applications, depending on the values of bits RD0 and RD1 in UCONFIG0 byte (see Table 13, Page 15). th A16 O 17 Address Bit Output to memory as 17th external address bit (A16) in extended bus applications, depending on the values of bits RD0 and RD1 in UCONFIG0 byte (see Table 13, Page 15) ...
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... PWR Digital Supply Voltage Connect this pin to +5V or +3V supply voltage. VPP I Programming Supply Voltage The programming supply voltage is applied to this input for programming the on-chip EPROM/ OTPROM. Rev May 7, 1999 TSC80251G2D Description 2 C data line. Alternate Function A15:8 P3.7 is applied, IH1 P3 ...
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... VSS2 GND Secondary Ground 2 This ground is provided to reduce ground bounce and improve power supply bypassing. Connection of this pin to ground is recommended. However, when using the TSC80251G2D as a pin-for-pin replacement for a 8xC51 product, VSS2 can be unconnected without loss of compatibility. Not available on DIP package. ...
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... If the program executes exclusively from on-chip code memory (not from external memory), beware of executing code from the upper eight bytes of the on-chip ROM (FF:7FF8h-FF:7FFFh). Because of its pipeline capability, the TSC80251G2D derivative may attempt to prefetch code from external memory (at an address above FF:7FFFh) and thereby disrupt I/O Ports 0 and 2. Fetching code constants from these 8 bytes does not affect Ports 0 and 2 ...
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... Kbytes are also mapped in the upper part of the region 00: if the On-Chip Code Memory Map configuration bit is cleared (EMAP# bit in UCONFIG1 byte, see Figure 8). However, if EA# is tied to a low level, the TSC80251G2D derivative is running as a ROMless product and the code is actually fetched in the corresponding external memory (i ...
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... RCAP2H Timer/Counter 2 Reload/Capture High Byte WDTRST WatchDog Timer Reset Table 6. Serial I/O Port SFRs Mnemonic Name SADDR Slave Address BRL Baud Rate Reload BDRCON Baud Rate Control Table 7. SSLC SFRs Mnemonic Name SSADR Synchronous Serial Address SSBR Synchronous Serial Bit Rate TSC80251G2D 11 ...
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... TSC80251G2D Mnemonic Name CCON EWC-PCA Timer/Counter Control CMOD EWC-PCA Timer/Counter Mode CL EWC-PCA Timer/Counter Low Register CH EWC-PCA Timer/Counter High Register CCAPM0 EWC-PCA Timer/Counter Mode 0 CCAPM1 EWC-PCA Timer/Counter Mode 1 CCAPM2 EWC-PCA Timer/Counter Mode 2 CCAPM3 EWC-PCA Timer/Counter Mode 3 CCAPM4 EWC-PCA Timer/Counter Mode 4 Mnemonic Name ...
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... Reserved Notes: 1. These registers are described in the TSC80251 Programmer’s Guide (C251 core registers and SPI modes, SSCON is splitted in two separate registers. SSCON reset value is 0000 0000 read and write modes, SSCS is splitted in two separate registers. SSCS reset value is 1111 1000 in read mode and 0000 0000 in write mode. ...
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... When EA# is tied to a low level, the configuration bytes are fetched from the external address space. The TSC80251G2D derivatives reserve the top eight bytes of the memory address space (FF:FFF8h-FF:FFFFh) for an external 8-byte configuration array. Only two bytes are actually used: UCONFIG0 at FF:FFF8h and UCONFIG1 at FF:FFF9h ...
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... Figure 8. Configuration Byte 1 PSEN# Read signal for all external memory locations Read signal for all external memory locations Read signal for all external memory locations Read signal for regions FE: and FF: TSC80251G2D WSB1# WSB0# EMAP# WR# External Memory Write signal for all external ...
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... A constant, equal that is immediately addressed in an instruction. Rev May 7, 1999 Non-Page Mode (states) 1 Wait State 2 Wait States Table 15. Notation for Direct Addressing Description Description TSC80251G2D 3 Wait States 4 Wait States ...
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... TSC80251G2D Direct Address A directly addressed bit (bit number= 00h-FFh) in memory or an SFR. Bits 00h-7Fh are bit51 the 128 bits in byte locations 20h-2Fh in the on-chip RAM. Bits 80h-FFh are the 128 bits in the 16 SFRs with addresses that end 8h, S:80h, S:88h, S:90h,..., S:F0h, S:F8h. ...
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... If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add addresses a Peripheral SFR this instruction addresses external memory location, add N+2 to the number of states (N: number of wait states this instruction addresses external memory location, add 2(N+2) to the number of states (N: number of wait states). Rev May 7, 1999 TSC80251G2D dest opnd dest opnd + src opnd dest opnd ...
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... TSC80251G2D Table 21. Summary of Increment and Decrement Instructions Increment INC <dest> Increment INC <dest>, <src> Decrement DEC <dest> Decrement DEC <dest>, <src> (1) Mnemonic <dest>, <src> A ACC Register by 1 INC DEC dir8 Direct address (on-chip RAM or SFR @Ri Indirect address by 1 Rm, #short ...
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... If this instruction addresses an I/O Port (Px, x= 0-3), add 2 to the number of states. Add addresses a Peripheral SFR this instruction addresses external memory location, add N+2 to the number of states (N: number of wait states this instruction addresses external memory location, add 2(N+2) to the number of states (N: number of wait states). Rev May 7, 1999 TSC80251G2D dest opnd dest opnd dest opnd ...
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... TSC80251G2D Table 24. Summary of Logical Instructions (2/2) Shift Left Logical SLL <dest> Shift Right Arithmetic SRA <dest> Shift Right Logical SRL <dest> Swap SWAP A (1) Mnemonic <dest>, <src> Rm Shift byte register left through the MSB SLL WRj Shift word register left through the MSB ...
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... Instructions that move bits are in Table 29. 2. Move instructions from the C51 Architecture this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add addresses a Peripheral SFR. 4. Apply note 3 for each dir8 operand. Rev May 7, 1999 TSC80251G2D dest opnd src opnd 31:16 dest opnd ...
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... TSC80251G2D Table 28. Summary of Move Instructions (3/3) (1) Move MOV <dest>, <src> (1) Mnemonic <dest>, <src> Rmd, Rms Byte register to byte register WRjd, WRjs Word register to word register DRkd, DRks Dword register to dword register Rm, #data Immediate 8-bit data to byte register WRj, #data16 Immediate 16-bit data to word register ...
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... If this instruction addresses an I/O Port (Px, x= 0-3), add 2 to the number of states. Add addresses a Peripheral SFR. Rev May 7, 1999 Table 29. Summary of Bit Instructions dest opnd dest opnd dest opnd (CY) (CY) (CY) (CY) (CY) dest opnd Comments TSC80251G2D 0 1 bit (CY) src opnd (CY) src opnd (CY) src opnd (CY) src opnd src opnd ...
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... TSC80251G2D Table 30. Summary of Exchange, Push and Pop Instructions Exchange bytes XCH A, <src> Exchange Digit XCHD A, <src> Push PUSH <src> Pop POP <dest> (1) Mnemonic <dest>, <src> ACC and register XCH A, dir8 ACC and direct address (on-chip RAM or SFR) A, @Ri ACC and indirect address ...
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... If this instruction addresses an I/O Port (Px, x= 0-3), add 3 to the number of states. Add addresses a Peripheral SFR internal execution only, add 1 to the number of states of the ‘jump taken’ if the destination address is internal and odd. Rev May 7, 1999 TSC80251G2D (PC) (PC) + size (instr); ...
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... TSC80251G2D Table 33. Summary of unconditional Jump Instructions Absolute jump Extended jump Long jump Short jump Jump indirect No operation (1) Mnemonic <dest>, <src> AJMP addr11 addr24 EJMP @DRk @WRj LJMP addr16 SJMP rel JMP @A +DPTR NOP Notes shaded cell denotes an instruction in the C51 Architecture. ...
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... EPROM/OTPROM devices. 8.1.3 ROMless Devices The TSC80251G2D products do not include on-chip Configuration Bytes, Code Memory and Encryption Array. They only include Signature Bytes made of Mask ROM cells which can be read using the same algorithm as the EPROM/OTPROM devices ...
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... TSC80251G2D 8.2.1 Lock Bit System The TSC87251G2D products implement 3 levels of security for User’s program as described in Table 35. The TSC83251G2D products implement only the first level of security. Level 0 is the level of an erased part and does not enable any security features. Level 1 locks the programming of the User’s internal Code Memory, the Configuration Bytes and the Encryption Array. Level 2 locks the verifying of the User’ ...
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... Signature Bytes The TSC80251G2D derivatives contain factory-programmed Signature Bytes. These bytes are located in non-volatile memory outside the memory address space at 30h, 31h, 60h and 61h. To read the Signature Bytes, perform the procedure described in section 8.5, using the verify signature mode (see Table 39). Signature byte values are listed in Table 37 ...
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... TSC80251G2D 100 s pulses Mode A[7:0] A[14:8] Data (1) ROM Area RST EA#/VPP On-chip Code Memory 1 Configuration Bytes 1 Lock Bits 1 Encryption Array 1 Notes: 1. Signature Bytes are not user-programmable. 2. The ALE/PROG# pulse waveform is shown in Figure 31 page 54. 8.5 Verify Algorithm Figure 10 shows the hardware setup needed to verify the TSC87251G2D EPROM/OTPROM or TSC83251G2D ROM areas: The chip has to be put under reset and maintained in this state until the completion of the verifying sequence ...
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... VDD RST VDD EA#/VPP ALE/PROG# PSEN# TSC8x251G2D P0[7:0] P2[7:0] P3[7:0] XTAL1 P1[7:0] VSS/VSS1/VSS2 Figure 10. Setup for Verifying TSC80251G2D P0 P2 P1(MSB) P3(LSB) 16-bit Address 28h Data 0000h-7FFFh (32 Kbytes) CONFIG0: FFF8h 29h Data CONFIG1: FFF9h 2Bh Data 0000h 29h Data 0030h, 0031h, 0060h, 0061h VDD ...
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... Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage. These are stress ratings only. Operation beyond the “operating conditions” is not recommended and extended exposure beyond the “Operating Conditions” may affect device reliability. Rev May 7, 1999 Table 40. Absolute Maximum Ratings -65 to +150 C -0 1.5 W Table 41. Operating Conditions 0 to +70 C -40 to +85 C 4.5 to 5.5 V 2.7 to 5.5 V TSC80251G2D 33 ...
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... TSC80251G2D 10. DC Characteristics - Commercial & Industrial 10.1 DC Characteristics: High Speed versions - Commercial & Industrial Table 42. DC Characteristics; V Symbol Parameter V Input Low Voltage IL (except EA#, SCL, SDA) (5) V Input Low Voltage IL1 (SCL, SDA) V Input Low Voltage IL2 (EA#) V Input high Voltage IH (except XTAL1, RST, SCL, SDA) ...
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... C. They are not tested and there is not guarantee on these values specification input voltage below 0.3·V will be recognized as a logic (1) Frequency at X (MHz) TAL . XTAL /I Versus Frequency TSC80251G2D will be recognized as a logic 4 ...
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... TSC80251G2D 10.2 DC Characteristics: Low Voltage versions - Commercial & Industrial Table 43. DC Characteristics; V Symbol Parameter V Input Low Voltage IL (except EA#, SCL, SDA) (5) V Input Low Voltage IL1 (SCL, SDA) V Input Low Voltage IL2 (EA#) V Input high Voltage IH (except XTAL1, RST, SCL, SDA) (5) V Input high Voltage ...
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... C. They are not tested and there is not guarantee on these values specification input voltage below 0.3·V will be recognized as a logic (1) Frequency at X (MHz) TAL . XTAL /I Versus X Frequency TAL TSC80251G2D will be recognized as a logic 2 ...
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... Test Condition, Active Mode DD RST VDD TSC80251G2D P0 (NC) XTAL2 EA# XTAL1 VSS All other pins are unconnected Figure 14. I Test Condition, Idle Mode DL RST VDD TSC80251G2D P0 (NC) XTAL2 EA# XTAL1 VSS All other pins are unconnected Test Condition, Power-Down Mode PD VDD I DD VDD VDD I DL ...
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... Timings Test conditions: capacitive load on all pins= 50 pF. Table 45 and Table 46 list the AC timing parameters for the TSC80251G2D derivatives with no wait states. External wait states can be added by extending PSEN#/RD#/WR# and or by extending ALE. In these tables, Note 2 marks parameters affected by one ALE wait state, and Note 3 marks parameters affected by PSEN#/RD#/WR# wait states. ...
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... TSC80251G2D Table 45. Bus Cycles AC Timings; V Symbol Parameter T 1/F OSC OSC T ALE Pulse Width LHLL T Address Valid to ALE Low AVLL T Address hold after ALE Low LLAX (1) T RD#/PSEN# Pulse Width RLRH T WR# Pulse Width WLWH (1) T ALE Low to RD#/PSEN# Low LLRL T ALE High to Address Hold ...
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... Specification for PSEN# are identical to those for RD wait state is added by extending ALE, add 2· wait states are added by extending RD#/PSEN#/WR#, add 2N·T Rev May 7, 1999 = 2 Parameter OSC. (N= 1..3). OSC TSC80251G2D = - MHz 16 MHz Min Max Min Max 83 ...
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... TSC80251G2D Waveforms in Non-Page Mode ALE PSEN# P0 P2/A16/A17 Note: 1. The value of this parameter depends on wait states. See Table 45 and Table 46. Figure 16. External Bus Cycle: Code Fetch (Non-Page Mode) ALE RD#/PSEN# P0 P2/A16/A17 Note: 1. The value of this parameter depends on wait states. See Table 45 and Table 46. ...
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... T LHLL (1) T LLRL (1) T RLDV T RLAZ (1) T LHAX ( AVLL LLAX A15:8 D7:0 Instruction In (1) T AVRL ( AVDV1 AXDX (1) T AVDV2 A7:0/A16/A17 (2) Page Miss ). TSC80251G2D T WHLH QVWH T WHQX D7:0 Data Out T WHAX T RHDZ1 T RHDX D7:0 Instruction In (1) T AVDV3 T RHAX A7:0/A16/A17 (2) Page Hit ); OSC 43 ...
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... TSC80251G2D ALE RD#/PSEN# P2 P0/A16/A17 Note: 1. The value of this parameter depends on wait states. See Table 45 and Table 46. Figure 20. External Bus Cycle: Data Read (Page Mode) ALE WR# P2 P0/A16/A17 Note: 1. The value of this parameter depends on wait states. See Table 45 and Table 46. Figure 21. External Bus Cycle: Data Write (Page Mode) ...
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... Figure 22. Real-time Synchronous Wait State: Code Fetch/Data Read Rev May 7, 1999 Min 2W·T 2W·T 2W·T State 2 State 3 min T CLYX T CLYV RD#/PSEN# stretched max min D7:0 stretched A15:8 stretched TSC80251G2D Conditions Low Valid No Longer Valid = 2 Max OSC + 5 (1+2W)· OSC OSC OSC + 5 (1+2W)·T ...
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... TSC80251G2D State 1 WCLK ALE RD#/PSEN# T WLYX T WLYX T WLYV WAIT# P0 A7:0 P2 Figure 23. Real-time Synchronous Wait State: Data Write 11.3 AC Characteristics - Real-Time Asynchronous Wait State Definition of symbols Table 49. Real-Time Asynchronous Wait Timing Symbol Definitions Signals S PSEN#/RD#/WR# Y AWAIT# Timings Table 50. Real-Time Asynchronous Wait AC Timings; V Symbol ...
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... MHz Min Max Min 998 749 833 625 165 124 0 974 XHDX Valid Valid Valid TSC80251G2D Conditions High Low Valid No Longer Valid = 2 (1) 16 MHz 24 MHz Unit Max Min Max 500 417 732 482 ...
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... TSC80251G2D 11.5 AC Characteristics - SSLC: I Timings 2 Table 53 Interface AC Timing; V Symbol T ; STA Start condition hold time HD T SCL low time LOW T SCL high time HIGH T SCL rise time RC T SCL fall time DAT1 Data set-up time DAT2 SDA set-up time (before repeated START condition) ...
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... Input Rise Time ILIH T Input Fall Time IHIL T Output Rise time OLOH T Output Fall Time OHOL Rev May 7, 1999 2 Parameter TSC80251G2D Conditions High Low Valid No Longer Valid Floating = - Min Max Unit 8 T OSC 3.2 T OSC 3.2 T OSC ...
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... TSC80251G2D Symbol (3) Master mode T Clock Period CHCH T Clock High Time CHCX T Clock Low Time CLCX Input Data Valid to Clock Edge IVCL IVCH Input Data Hold after Clock Edge CLIX CHIX T T Output Data Valid after Clock Edge CLOV, CHOV ...
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... SLCH T CHCH SLCL T T CHCX CLCX T CLOV T SLOV T CHOV SLAVE MSB OUT BIT IVCH CHIX T T IVCL CLIX MSB IN BIT 6 TSC80251G2D T CLCH T CHCL LSB IN LSB OUT Port Data T CLSH T T SHSL CHSH T CLCH T CHCL T CLOX T SHOX T CHOX (1) SLAVE LSB OUT ...
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... TSC80251G2D SS# (input SCK (SSCPOL= 0) (input) SCK (SSCPOL= 1) (input) MISO (output) MOSI (input) Note: 1. Not Defined but generally the LSB of the character which has just been received. Figure 30. SPI Slave Waveforms (SSCPHA SLCH T CHCH SLCL T T CHCX CLCX T CHOV T SLOV ...
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... Address to Data Invalid AXQX T ENABLE low to Data Valid ELQV T Data Float after ENABLE EHQZ Rev May 7, 1999 4 Parameter PP = 4 Parameter TSC80251G2D Conditions High Low Valid No Longer Valid Floating = Min Max Unit 83.5 250 OSC 48 T OSC 48 ...
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... TSC80251G2D Waveforms P1= A15:8 P3= A7:0 P2= D7 EA#/VPP ALE/PROG# T ELSH P0 Figure 31. EPROM Programming Waveforms P1= A15:8 P3= A7:0 P2= D7:0 P0 Figure 32. EPROM Verifying Waveforms 54 Address T AVGL Data T T DVGL GHDX T T SHGL GLGH Mode= 68h, 69h, 6Bh or 6Ch Address T AVQV Data T ELQV Mode= 28h, 29h or 2Bh ...
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... Figure 33. External Clock Waveform 0 0 0.1 DD -0.5 V for a logic 1 and 0.45 V for a logic 0. DD min for a logic 1 and V max for a logic Timing Reference Points / mA Figure 35. Float Waveforms TSC80251G2D Conditions High Low No Longer Valid = - Min Max CHCX CLCL OUTPUTS V ...
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... E1 12. 2.93 D1 0.13 Rev May 7, 1999 Figure 36. Plastic Dual In Line Table 61. PDIL Package Size MM Max 5.08 - 4.95 0.56 1.78 0.38 53.21 15.87 14.73 2.54 B.S.C. 15.24 B.S.C. 17.78 3.81 - TSC80251G2D INCH Min Max - .200 .015 - .125 .195 .014 .022 .030 .070 .008 .015 1.980 2.095 .600 .625 .485 .580 .100 B.S.C. .600 B.S.C. - .700 .115 .150 .005 ...
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... TSC80251G2D 12.3 CDIL 40 with Window - Mechanical Outline Min 0.36 b2 1. 13. 3.18 Q 0. Figure 37. Ceramic Dual In Line Table 62. CDIL Package Size MM Max 5.71 0.58 1.65 0.38 53.47 15.37 2.54 B.S.C. 15.24 B.S.C. 5.08 1. INCH Min Max - .225 .014 .023 .045 .065 .008 .015 - 2.105 .514 .605 .100 B.S.C. .600 B.S.C. .125 .200 ...
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... Nd Ne Rev May 7, 1999 Figure 38. Plastic Lead Chip Carrier Table 63. PLCC Package Size MM Max 4.57 3.04 17.65 16.66 16.00 17.65 16.66 16.00 1.27 BSC 1.22 1. TSC80251G2D INCH Min Max .165 .180 .090 .120 .685 .695 .647 .656 .590 .630 .685 .695 .647 .656 .590 .630 .050 BSC .042 .048 .042 ...
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... TSC80251G2D 12.5 CQPJ 44 with Window - Mechanical Outline Min 0. 17. 16. 0.43 J 0.86 Q 15. Figure 39. Ceramic Quad Pack J Table 64. CQPJ Package size MM Max 4.90 0.25 17.55 16.66 1.27 TYP 0.53 1.12 16.00 0.86 TYP 11 11 INCH Min Max - .193 .006 .010 .685 .691 .644 .656 .050 TYP .017 .021 .034 ...
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... D 11.90 D1 9.90 E 11.90 E1 9.90 J 0. Rev May 7, 1999 Table 65. VQFP Package Size MM Max 1.60 0.64 REF 0.64 REF 1.45 12.10 10.10 12.10 10.10 - 0.75 0.80 BSC 0.35 BSC TSC80251G2D INCH Min Max - .063 .025 REF .025REF .053 .057 .468 .476 .390 .398 .468 .476 .390 .398 .002 6 .018 .030 .0315 BSC .014 BSC 60 ...
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... Ordering Information 13.1 TSC80251G2D ROMless TEMIC Part Number High Speed Versions 4.5 to 5.5 V, Commercial and Industrial TSC80251G2D-16CB TSC80251G2D-24CB TSC80251G2D-24CED TSC80251G2D-24IA TSC80251G2D-24IB Low Voltage Versions 2.7 to 5.5 V, Commercial TSC80251G2D-L16CB TSC80251G2D-L16CED Note: 1. Dry Pack mandatory for VQFP package. 13.2 TSC83251G1D 16 Kbytes Mask ROM (2) TEMIC Part Number High Speed Versions 4.5 to 5.5 V, Commercial and Industrial ...
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... TEMIC sales) ROM code encryption Tape & Real or Dry Pack Known good dice Ceramic packages Extended temperature range: - +125 C 13.7 Starter Kit TEMIC Part Number TSC80251-SK 13.8 Products Marking ROMless versions Mask ROM versions TEMIC TEMIC (1) Temic Part number Customer Part number Temic Part number INTEL’ ...
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Sales Locations Europe Sales Offices Finland Germany TEMIC Nordic AB TEMIC Semiconductor c/o Atmel OY GmbH Kappelitie 6B Erfurter Strasse 31 FIN–02200 85386 Eching Tel: 358 9 4520 8219 Tel Fax: 358 9 529 ...