MC9S08AW60 FREESCALE [Freescale Semiconductor, Inc], MC9S08AW60 Datasheet - Page 228

• Manufacturer Part Number: MC9S08AW60
• Description: Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Chapter 13 Inter-Integrated Circuit (S08IICV1)
13.4.1.8
The clock synchronization mechanism can be used as a handshake in data transfer. Slave devices may hold
the SCL low after completion of one byte transfer (9 bits). In such case, it halts the bus clock and forces
the master clock into wait states until the slave releases the SCL line.
13.4.1.9
The clock synchronization mechanism can be used by slaves to slow down the bit rate of a transfer. After
the master has driven SCL low the slave can drive SCL low for the required period and then release it. If
the slave SCL low period is greater than the master SCL low period then the resulting SCL bus signal low
period is stretched.
13.5
The IIC is disabled after reset. The IIC cannot cause an MCU reset.
13.6
The IIC generates a single interrupt.
An interrupt from the IIC is generated when any of the events in
is set. The interrupt is driven by bit IICIF (of the IIC status register) and masked with bit IICIE (of the IIC
control register). The IICIF bit must be cleared by software by writing a one to it in the interrupt routine.
The user can determine the interrupt type by reading the status register.
228
Resets
Interrupts
SCL1
SCL2
SCL
Handshaking
Clock Stretching
Match of received calling address
Complete 1-byte transfer
Interrupt Source
INTERNAL COUNTER RESET
Arbitration Lost
Figure 13-9. IIC Clock Synchronization
Table 13-7. Interrupt Summary
MC9S08AW60 Data Sheet, Rev 2
DELAY
Status
ARBL
IAAS
TCF
Table 13-7
IICIF
IICIF
IICIF
Flag
START COUNTING HIGH PERIOD
Local Enable
occur provided the IICIE bit
IICIE
IICIE
IICIE
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