AT91RM3400-AI-001 ATMEL [ATMEL Corporation], AT91RM3400-AI-001 Datasheet - Page 81

• Manufacturer Part Number: AT91RM3400-AI-001
• Manufacturer: ATMEL [ATMEL Corporation]

Functional Description
Bus Arbiter
Address Decoder
1790A–ATARM–11/03
The Memory Controller handles the internal ASB bus and arbitrates the accesses of
both masters.
It is made up of:
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•
•
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The MC handles only little-endian mode accesses. The masters work in little-endian
mode only.
The Memory Controller has a simple, hard-wired priority bus arbiter that gives the con-
trol of the bus to one of the two masters. The Peripheral Data Controller has the highest
priority; the ARM processor has the lowest one.
The Memory Controller features an Address Decoder that first decodes the four highest
bits of the 32-bit address bus and defines three separate areas:
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Figure 22 shows the assignment of the 256-Mbyte memory areas.
Figure 22. Memory Areas
A bus arbiter
An address decoder
An abort status
A misalignment detector
A memory protection unit
One 256-Mbyte address space for the internal memories
One 256-Mbyte address space reserved for the embedded peripherals
An undefined address space of 3584M bytes representing fourteen 256-Mbyte
areas that return an Abort if accessed
14 x 256MBytes
256M Bytes
256M Bytes
3,584 Mbytes
0x0000 0000
0xF000 0000
0x0FFF FFFF
0xEFFF FFFF
0xFFFF FFFF
0x1000 0000
Internal Memories
Peripherals
Undefined
(Abort)
AT91RM3400
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