AT91RM3400-AI-001 ATMEL [ATMEL Corporation], AT91RM3400-AI-001 Datasheet - Page 210

• Manufacturer Part Number: AT91RM3400-AI-001
• Manufacturer: ATMEL [ATMEL Corporation]

Input Change
Interrupt
210
AT91RM3400
The PIO Controller can be programmed to generate an interrupt when it detects an input
change on an I/O line. The Input Change Interrupt is controlled by writing PIO_IER (Interrupt
Enable Register) and PIO_IDR (Interrupt Disable Register), which respectively enable and
disable the input change interrupt by setting and clearing the corresponding bit in PIO_IMR
(Interrupt Mask Register). As Input change detection is possible only by comparing two suc-
cessive samplings of the input of the I/O line, the PIO Controller clock must be enabled. The
Input Change Interrupt is available, regardless of the configuration of the I/O line, i.e. config-
ured as an input only, controlled by the PIO Controller or assigned to a peripheral function.
When an input change is detected on an I/O line, the corresponding bit in PIO_ISR (Interrupt
Status Register) is set. If the corresponding bit in PIO_IMR is set, the PIO Controller interrupt
line is asserted. The interrupt signals of the thirty-two channels are ORed-wired together to
generate a single interrupt signal to the Advanced Interrupt Controller.
When the software reads PIO_ISR, all the interrupts are automatically cleared. This signifies
that all the interrupts that are pending when PIO_ISR is read must be handled.
Figure 70. Input Change Interrupt Timings
Read PIO_ISR
PIO_PDSR
PIO_ISR
MCK
APB Access
APB Access
1790A–ATARM–11/03