AT91RM3400-AI-001 ATMEL [ATMEL Corporation], AT91RM3400-AI-001 Datasheet - Page 160

• Manufacturer Part Number: AT91RM3400-AI-001
• Manufacturer: ATMEL [ATMEL Corporation]

ST Period Interval Mode Register
Register Name: ST_PIMR
Access Type:
• PIV: Period Interval Value
Defines the value loaded in the 16-bit counter of the period interval timer. The maximum period is obtained by programming
PIV at 0x0 corresponding to 65536 slow clock cycles.
ST Watchdog Mode Register
Register Name: ST_WDMR
Access Type:
• WDV: Watchdog Counter Value
Defines the value loaded in the 16-bit counter. The maximum period is obtained by programming WDV to 0x0 correspond-
ing to 65536 x 128 slow clock cycles.
• RSTEN: Reset Enable
0 = No reset is generated when a watchdog overflow occurs.
1 = An internal reset is generated when a watchdog overflow occurs.
• EXTEN: External Signal Assertion Enable
0 = The watchdog_overflow is not tied low when a watchdog overflow occurs.
1 = The watchdog_overflow is tied low during 8 slow clock cycles when a watchdog overflow occurs.
160
31
23
15
–
–
–
–
7
AT91RM3400
Read/Write
Read/Write
30
22
14
–
–
–
–
6
29
21
13
–
–
–
–
5
28
20
12
–
–
–
–
4
WDV
WDV
PIV
PIV
27
19
11
–
–
–
–
3
26
18
10
–
–
–
–
2
EXTEN
25
17
–
–
–
9
1
1790A–ATARM–11/03
RSTEN
24
16
–
–
–
8
0