PIC24FJ128GB MICROCHIP [Microchip Technology], PIC24FJ128GB Datasheet - Page 34
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PIC24FJ128GB
Manufacturer Part Number
PIC24FJ128GB
Description
64/80/100-Pin, 16-Bit Flash Microcontrollers with USB On-The-Go (OTG)
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.PIC24FJ128GB.pdf
(328 pages)
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PIC24FJ256GB110 FAMILY
3.1.1
The
word-addressable blocks. Although it is treated as
24 bits wide, it is more appropriate to think of each
address of the program memory as a lower and upper
word, with the upper byte of the upper word being
unimplemented. The lower word always has an even
address, while the upper word has an odd address
(Figure 3-2).
Program memory addresses are always word-aligned
on the lower word, and addresses are incremented or
decremented by two during code execution. This
arrangement also provides compatibility with data
memory space addressing and makes it possible to
access data in the program memory space.
3.1.2
All PIC24F devices reserve the addresses between
00000h and 000200h for hard coded program execu-
tion vectors. A hardware Reset vector is provided to
redirect code execution from the default value of the
PC on device Reset to the actual start of code. A GOTO
instruction is programmed by the user at 000000h with
the actual address for the start of code at 000002h.
PIC24F devices also have two interrupt vector tables,
located from 000004h to 0000FFh and 000100h to
0001FFh. These vector tables allow each of the many
device interrupt sources to be handled by separate
ISRs. A more detailed discussion of the interrupt vector
tables is provided in Section 6.1 “Interrupt Vector
Table”.
FIGURE 3-2:
DS39897B-page 32
program
000001h
000003h
000005h
000007h
Address
MSW
PROGRAM MEMORY
ORGANIZATION
HARD MEMORY VECTORS
memory
Program Memory
PROGRAM MEMORY ORGANIZATION
‘Phantom’ Byte
(read as ‘0’)
00000000
00000000
00000000
00000000
space
most significant word
is
23
organized
Preliminary
in
16
Instruction Width
3.1.3
In PIC24FJ256GB110 family devices, the top three
words of on-chip program memory are reserved for
configuration information. On device Reset, the config-
uration information is copied into the appropriate
Configuration registers. The addresses of the Flash
Configuration
PIC24FJ256GB110 family are shown in Table 3-1.
Their location in the memory map is shown with the
other memory vectors in Figure 3-1.
The Configuration Words in program memory are a
compact format. The actual Configuration bits are
mapped in several different registers in the configuration
memory space. Their order in the Flash Configuration
Words do not reflect a corresponding arrangement in the
configuration space. Additional details on the device
Configuration Words are provided in Section 25.1
“Configuration Bits”.
TABLE 3-1:
PIC24FJ64GB
PIC24FJ128GB
PIC24FJ192GB
PIC24FJ256GB
least significant word
Device
8
FLASH CONFIGURATION WORDS
Word
FLASH CONFIGURATION
WORDS FOR
PIC24FJ256GB110 FAMILY
DEVICES
Program
Memory
(Words)
22,016
44,032
67,072
87,552
© 2008 Microchip Technology Inc.
for
0
(LSW Address)
devices
PC Address
000000h
000002h
000004h
000006h
Configuration
Addresses
00ABFAh:
02ABFAh:
020BFAh:
00ABFEh
0157FAh:
02ABFEh
020BFEh
0157FEh
Word
in
the
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