PIC24FJ128GB MICROCHIP [Microchip Technology], PIC24FJ128GB Datasheet - Page 173
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PIC24FJ128GB
Manufacturer Part Number
PIC24FJ128GB
Description
64/80/100-Pin, 16-Bit Flash Microcontrollers with USB On-The-Go (OTG)
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.PIC24FJ128GB.pdf
(328 pages)
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To set up the SPI module for the Enhanced Buffer
Master mode of operation:
1.
2.
3.
4.
5.
6.
FIGURE 14-2:
© 2008 Microchip Technology Inc.
SSx/FSYNCx
If using interrupts:
a)
b)
c)
Write the desired settings to the SPIxCON1 and
SPIxCON2
(SPIxCON1<5>) = 1.
Clear the SPIROV bit (SPIxSTAT<6>).
Select Enhanced Buffer mode by setting the
SPIBEN bit (SPIxCON2<0>).
Enable SPI operation by setting the SPIEN bit
(SPIxSTAT<15>).
Write the data to be transmitted to the SPIxBUF
register. Transmission (and reception) will start
as soon as data is written to the SPIxBUF
register.
SDOx
SCKx
SDIx
Clear the SPIxIF bit in the respective IFS
register.
Set the SPIxIE bit in the respective IEC
register.
Write the SPIxIP bits in the respective IPC
register.
Read SPIxBUF
Control
registers
Transfer
Sync
SPIx MODULE BLOCK DIAGRAM (ENHANCED MODE)
Receive Buffer
8-Level FIFO
bit0
with
SPIxSR
Control
SPIxBUF
Clock
Shift Control
Transmit Buffer
8-Level FIFO
MSTEN
PIC24FJ256GB110 FAMILY
Preliminary
Transfer
Write SPIxBUF
Select
Edge
To set up the SPI module for the Enhanced Buffer
Slave mode of operation:
1.
2.
3.
4.
5.
6.
7.
8.
16
Clear the SPIxBUF register.
If using interrupts:
a)
b)
c)
Write the desired settings to the SPIxCON1 and
SPIxCON2
(SPIxCON1<5>) = 0.
Clear the SMP bit.
If the CKE bit is set, then the SSEN bit must be
set, thus enabling the SSx pin.
Clear the SPIROV bit (SPIxSTAT<6>).
Select Enhanced Buffer mode by setting the
SPIBEN bit (SPIxCON2<0>).
Enable SPI operation by setting the SPIEN bit
(SPIxSTAT<15>).
Secondary
Clear the SPIxIF bit in the respective IFS
register.
Set the SPIxIE bit in the respective IEC
register.
Write the SPIxIP bits in the respective IPC
register to set the interrupt priority.
Prescaler
1:1 to 1:8
Internal Data Bus
registers
1:1/4/16/64
Prescaler
Primary
with
DS39897B-page 171
SPIxCON1<1:0>
SPIxCON1<4:2>
Enable
Master Clock
F
CY
MSTEN
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