PIC24FJ128GB MICROCHIP [Microchip Technology], PIC24FJ128GB Datasheet - Page 207

• Manufacturer Part Number: PIC24FJ128GB
• Description: 64/80/100-Pin, 16-Bit Flash Microcontrollers with USB On-The-Go (OTG)
• Manufacturer: MICROCHIP [Microchip Technology]

17.6.2
In USB OTG applications, a Dual Role Device (DRD) is
a device that is capable of being either a host or a
peripheral. Any OTG DRD must support Host
Negotiation Protocol (HNP).
HNP allows an OTG B-device to temporarily become
the USB host. The A-device must first enable the
B-device to follow HNP. Refer to the On-The-Go Sup-
plement to the USB 2.0 Specification for more informa-
tion regarding HNP. HNP may only be initiated at full
speed.
After being enabled for HNP by the A-device, the
B-device requests being the host any time that the USB
link is in Suspend state, by simply indicating a discon-
nect. This can be done in software by clearing
DPPULUP and DMPULUP. When the A-device detects
the disconnect condition (via the URSTIF (U1IR<0>)
interrupt), the A-device may allow the B-device to take
over as Host. The A-device does this by signaling con-
nect as a full-speed function. Software may accomplish
this by setting DPPULUP.
If the A-device responds instead with resume signaling,
the A-device remains as host. When the B-device
detects
(U1IR<6>), the B-device becomes host. The B-device
drives Reset signaling prior to using the bus.
When the B-device has finished in its role as Host, it
stops all bus activity and turns on its D+ pull-up resistor
by setting DPPULUP. When the A-device detects a
suspend condition (Idle for 3 ms), the A-device turns off
its D+ pull-up. The A-device may also power-down
V
detects the connect condition (via ATTACHIF), the
A-device resumes host operation, and drives Reset
signaling.
© 2008 Microchip Technology Inc.
BUS
supply to end the session. When the A-device
the
HOST NEGOTIATION PROTOCOL
(HNP)
connect
condition
(via
ATTACHIF
PIC24FJ256GB110 FAMILY
Preliminary
17.7
There are a total of 37 memory mapped registers asso-
ciated with the USB OTG module. They can be divided
into four general categories:
• USB OTG Module Control (12)
• USB Interrupt (7)
• USB Endpoint Management (16)
• USB V
This total does not include the (up to) 128 BD registers
in
Register 17-1 and Register 17-2, are shown separately
in Section 17.1 “USB Buffer Descriptors and the
BDT”.
With the exception U1PWMCON and U1PWMRRS, all
USB OTG registers are implemented in the Least Sig-
nificant Byte of the register. Bits in the upper byte are
unimplemented, and have no function. Note that some
registers are instantiated only in Host mode, while
other registers have different bit instantiations and
functions in Device and Host modes.
Registers described in the following sections are those
that have bits with specific control and configuration
features. The following registers are used for data or
address values only:
• U1BDTP1: Specifies the 256-word page in data
• U1FRML and U1FRMH: Contains the 11-bit byte
• U1PWMRRS: Contains the 8-bit value for PWM
RAM used for the BDT; 8-bit value with bit 0 fixed
as ‘0’ for boundary alignment
counter for the current data frame
duty cycle (bits 15:8) and PWM period (bits 7:0)
for the V
the
USB OTG Module Registers
BUS
BDT.
BUS
Power Control (2)
boost assist PWM module.
Their
prototypes,
DS39897B-page 205
described
in