PIC24FJ128GB MICROCHIP [Microchip Technology], PIC24FJ128GB Datasheet - Page 163

• Manufacturer Part Number: PIC24FJ128GB
• Description: 64/80/100-Pin, 16-Bit Flash Microcontrollers with USB On-The-Go (OTG)
• Manufacturer: MICROCHIP [Microchip Technology]

13.2
In Compare mode (Figure 13-1), the output compare
module can be configured for single-shot or continuous
pulse generation; it can also repeatedly toggle an
output pin on each timer event.
To set up the module for compare operations:
1.
2.
3.
4.
5.
6.
7.
8.
© 2008 Microchip Technology Inc.
Configure the OCx output for one of the
available Peripheral Pin Select pins.
Calculate the required values for the OCxR and
(for Double Compare modes) OCxRS duty cycle
registers:
a)
b)
c)
Write the rising edge value to OCxR, and the
falling edge value to OCxRS.
Set the Timer Period register, PRy, to a value
equal to or greater than the value in OCxRS.
Set the OCM2:OCM0 bits for the appropriate
compare operation (= 0xx).
For Trigger mode operations, set OCTRIG to
enable Trigger mode. Set or clear TRIGMODE to
configure trigger operation, and TRIGSTAT to
select a hardware or software trigger. For
Synchronous mode, clear OCTRIG.
Set
configure the trigger or synchronization source.
If free-running timer operation is required, set
the SYNCSEL bits to ‘00000’ (no sync/trigger
source).
Select
OCTSEL2:OCTSEL0 bits. If necessary, set the
TON bit for the selected timer which enables the
compare time base to count. Synchronous mode
operation starts as soon as the time base is
enabled; Trigger mode operation starts after a
trigger source event occurs.
Compare Operations
Determine the instruction clock cycle time.
Take into account the frequency of the
external clock to the timer source (if one is
used) and the timer prescaler settings.
Calculate time to the rising edge of the out-
put pulse relative to the timer start value
(0000h).
Calculate the time to the falling edge of the
pulse based on the desired pulse width and
the time to the rising edge of the pulse.
the
the
SYNCSEL4:SYNCSEL0
time
base
source
with
bits
PIC24FJ256GB110 FAMILY
the
to
Preliminary
For 32-bit cascaded operation, these steps are also
necessary:
1.
2.
3.
4.
5.
6.
Depending on the output mode selected, the module
holds the OCx pin in its default state, and forces a tran-
sition to the opposite state when OCxR matches the
timer. In Double Compare modes, OCx is forced back
to its default state when a match with OCxRS occurs.
The OCxIF interrupt flag is set after an OCxR match in
Single Compare modes, and after each OCxRS match
in Double Compare modes.
Single-shot pulse events only occur once, but may be
repeated by simply rewriting the value of the
OCxCON1 register. Continuous pulse events continue
indefinitely until terminated.
Set
(OCyCON2<8> and (OCxCON2<8>). Enable
the even-numbered module first to ensure the
modules will start functioning in unison.
Clear the OCTRIG bit of the even module
(OCyCON2),
Synchronous mode.
Configure the desired output and Fault settings
for OCy.
Force the output pin for OCx to the output state
by clearing the OCTRIS bit.
If Trigger mode operation is required, configure
the trigger options in OCx by using the OCTRIG
(OCxCON2<7>), TRIGSTAT (OCxCON2<6>),
and SYNCSEL (OCxCON2<4:0>) bits.
Configure the desired compare or PWM mode of
operation (OCM<2:0>) for OCy first, then for
OCx.
the
OC32
so the module will
bits
for
DS39897B-page 161
both
registers
run
in