PIC24FJ16MC101-I/P Microchip Technology, PIC24FJ16MC101-I/P Datasheet
PIC24FJ16MC101-I/P
Specifications of PIC24FJ16MC101-I/P
Related parts for PIC24FJ16MC101-I/P
PIC24FJ16MC101-I/P Summary of contents
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... High-Performance, Ultra Low Cost © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 16-bit Microcontrollers Preliminary Data Sheet DS39997B ...
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... Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2011, Microchip Technology Incorporated, Printed in the U ...
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... PWM frequency for 11-bit resolution (@ 16 MIPS) = 15.63 kHz for Edge-Aligned mode, 7.81 kHz for Center-Aligned mode © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 Power Management: • Single supply on-chip voltage regulator • Switch between clock sources in real time • Idle, Sleep, and Doze modes with fast wake-up Analog Peripherals: • ...
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... PIC24FJ16MC101/102 Timers/Capture/Compare/PWM: • Timer/Counters three 16-bit timers: - Can pair up to make one 32-bit timer - One timer runs as Real-Time Clock with external 32.768 kHz oscillator - Programmable prescaler • Input Capture (up to three channels): - Capture on up, down, or both edges - 16-bit capture input functions - 4-deep FIFO on each capture • ...
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... PIC24FJ16MC101/102 PRODUCT FAMILIES The device names, pin counts, memory sizes, and peripheral availability of each device are listed in Table 1. The following pages show their pinout diagrams. TABLE 1: PIC24FJ16MC101/102 CONTROLLER FAMILIES Device PIC24FJ16MC101 PIC24FJ16MC102 Note 1: Two out of three timers are remappable. 2: Two out of three interrupts are remappable. ...
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... PIC24FJ16MC101/102 Pin Diagrams 20-Pin PDIP/SOIC/SSOP PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0 PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1 PGED1/AN2/C2INA/C1INC/RP0 PGEC1/AN3/CV /CV /C2INB/C1IND/RP1 REFIN REFOUT OSCO/CLKO/CN29/RA3 PGED3/SOSCI/RP4 PGEC3/SOSCO/T1CK/CN0/RA4 28-Pin SPDIP/SOIC/SSOP PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0 PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1 PGED1/AN2/C2INA/C1INC/RP0 PGEC1/AN3/CV /CV /C2INB/C1IND/RP1 REFIN REFOUT AN4/C3INC/C2INC/RP2 AN5/C3IND/C2IND/RP3 OSCO/CLKO/CN29/RA3 PGED3/SOSCI/RP4 PGEC3/SOSCO/T1CK/CN0/RA4 (2) FLTB1 /ASDA1/RP5 Note 1: The RPn pins can be used by any remappable peripheral. See peripherals ...
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... The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to V externally The PWM Fault pins are enabled and asserted during any reset event. Refer to “PWM Faults” for more information on the PWM faults. © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 (1) /CN4/RB0 ...
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... PIC24FJ16MC101/102 Pin Diagrams (Continued) 36-Pin TLA PGED1/AN2/C2INA/C1INC/RP0 PGEC1/AN3/ CV /CV /C2INB/C1IND/RP1 REFIN REFOUT AN4/C3INC/C2INC/RP2 AN5/C3IND/C2IND/RP3 OSCI/CLKI/CN30/RA2 OSCO/CLKO/CN29/RA3 PGED3/SOSCI/RP4 Note 1: The RPn pins can be used by any remappable peripheral. See peripherals. 2: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to V externally ...
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... Table of Contents PIC24FJ16MC101/102 Product Families............................................................................................................................................... 5 1.0 Device Overview ........................................................................................................................................................................ 11 2.0 Guidelines for Getting Started with 16-bit Microcontrollers ........................................................................................................ 17 3.0 CPU............................................................................................................................................................................................ 21 4.0 Memory Organization ................................................................................................................................................................. 27 5.0 Flash Program Memory.............................................................................................................................................................. 51 6.0 Resets ....................................................................................................................................................................................... 55 7.0 Interrupt Controller ..................................................................................................................................................................... 63 8.0 Oscillator Configuration .............................................................................................................................................................. 93 9.0 Power-Saving Features............................................................................................................................................................ 101 10.0 I/O Ports ................................................................................................................................................................................... 107 11 ...
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... PIC24FJ16MC101/102 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. ...
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... Harvard architecture, first introduced with ® Microchip’s dsPIC digital signal controllers. Figure 1-1 shows a general block diagram of the core and peripheral modules in the PIC24FJ16MC101/102 family of devices. Table 1-1 lists the functions of the various pins shown in the pinout diagrams. © 2011 Microchip Technology Inc. ...
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... PIC24FJ16MC101/102 FIGURE 1-1: PIC24FJ16MC101/102 BLOCK DIAGRAM PSV and Table Data Access Control Block Interrupt Controller 8 23 PCU PCH PCL 23 Program Counter Stack Control Logic 23 Address Latch Program Memory Data Latch 24 Instruction Decode and Control Control Signals to Various Blocks Power-up Timing OSC2/CLKO ...
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... Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels PPS = Peripheral Pin Select Note 1: An external pull-down resistor is required for the FLTA1 pin on PIC24FJ16MC101 (20-pin) devices. 2: The FLTB1 pin is not available on PIC24FJ16MC101 (20-pin) devices. 3: The PWM Fault pins are enabled during any reset event. Refer to information on the PWM faults. © ...
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... Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels PPS = Peripheral Pin Select Note 1: An external pull-down resistor is required for the FLTA1 pin on PIC24FJ16MC101 (20-pin) devices. 2: The FLTB1 pin is not available on PIC24FJ16MC101 (20-pin) devices. 3: The PWM Fault pins are enabled during any reset event. Refer to information on the PWM faults ...
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... Section 33. “Programming and Diagnostics” (DS39716) • Section 46. “10-bit Analog-to-Digital Converter (ADC) with 4 Simultaneous Conversions” (DS39737) • Section 47. “Motor Control PWM” (DS39735) • Section 48. “Comparator with Blanking” (DS39741) © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 web site 2 C™)” (DS39702) ...
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... PIC24FJ16MC101/102 Notes: DS39997B-page 16 Preliminary © 2011 Microchip Technology Inc. ...
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... Basic Connection Requirements Getting started with the PIC24FJ16MC101/102 family of 16-bit microcontrollers (MCUs) requires attention to a minimal set of device pin connections before proceeding with development. The following is a list of pin names, which must always be connected: • ...
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... PIC24FJ16MC101/102 FIGURE 2-1: RECOMMENDED MINIMUM CONNECTION 10 µ Tantalum R R1 MCLR C PIC24F 0.1 µF Ceramic 0.1 µF 10 Ω Ceramic 2.2.1 TANK CAPACITORS On boards with power traces running longer than six inches in length suggested to use a tank capacitor for integrated circuits including MCUs to supply a local power source ...
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... User’s Guide” (DS51616) ® • “Using MPLAB REAL ICE™” (poster) (DS51749) © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 2.6 External Oscillator Pins Many MCUs have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Configuration” ...
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... PIC24FJ16MC101/102 2.7 Oscillator Value Conditions on Device Start-up If the PLL of the target device is enabled and configured for the device start-up oscillator, the maximum oscillator source frequency must be limited to 4 MHz < F < 8 MHz (for MSPLL mode MHz < < 8 MHz (for ECPLL mode) to comply with device IN PLL start-up conditions ...
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... The data space also includes 2 Kbytes of DMA RAM, which is primarily used for DMA data transfers, but may be used as general purpose RAM. 3.2 Special MCU Features The PIC24FJ16MC101/102 features a 17-bit by 17-bit, single-cycle multiplier. The multiplier can perform A single-cycle signed, unsigned and mixed-sign multiplication. Using ...
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... PIC24FJ16MC101/102 FIGURE 3-1: PIC24FJ16MC101/102 CPU CORE BLOCK DIAGRAM PSV and Table Data Access Control Block Interrupt Controller 8 23 PCU 23 Program Counter Stack Control Logic 23 Address Latch Program Memory Data Latch 24 Instruction Decode and Control Control Signals to Various Blocks DS39997B-page 22 X Data Bus ...
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... FIGURE 3-2: PIC24FJ16MC101/102 PROGRAMMER’S MODEL PC22 0 7 TBLPAG Data Table Page Address 7 0 PSVPAG — — — — — — SRH © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 D15 D0 W0/WREG W10 W11 W12 W13 W14/Frame Pointer W15/Stack Pointer SPLIM PC0 0 Program Space Visibility Page Address ...
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... PIC24FJ16MC101/102 3.3 CPU Control Registers REGISTER 3-1: SR: CPU STATUS REGISTER U-0 U-0 U-0 — — — bit 15 (1) (2) R/W-0 R/W-0 R/W-0 (2) IPL<2:0> bit 7 Legend Clear only bit R = Readable bit S = Set only bit W = Writable bit ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-9 Unimplemented: Read as ‘ ...
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... Program space visible in data space 0 = Program space not visible in data space bit 1-0 Unimplemented: Read as ‘0’ Note 1: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level. © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 U-0 U-0 U-0 — — — ...
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... PIC24FJ16MC101/102 3.4 Arithmetic Logic Unit (ALU) The PIC24FJ16MC101/102 ALU is 16 bits wide and is capable of addition, subtraction, bit shifts, and logic operations. Unless otherwise mentioned, arithmetic operations are 2’s complement in nature. Depending on the operation, the ALU may affect the values of the Carry (C), Zero (Z), Negative (N), Overflow (OV), and Digit Carry (DC) Status bits in the SR register ...
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... The exception is the use of TBLRD/TBLWT operations, which use TBLPAG<7> to permit access to the Configuration bits and Device ID sections of the configuration memory space. The memory map for the PIC24FJ16MC101/102 family of devices is shown in 0x000000 GOTO Instruction 0x000002 ...
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... A GOTO instruction is programmed by the user application at 0x000000, with the actual address for the start of code at 0x000002. 4-2). PIC24FJ16MC101/102 devices also have two interrupt vector tables, located from 0x000004 to 0x0000FF and 0x000100 to 0x0001FF. These vector tables allow each of the device interrupt sources to be handled by sepa- rate Interrupt Service Routines (ISRs) ...
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... Data Address Space The PIC24FJ16MC101/102 CPU has a separate 16- bit-wide data memory space. The data space is accessed using separate Address Generation Units (AGUs) for read and write operations. The data memory maps is shown in Figure 4-3. All Effective Addresses (EAs) in the data memory space are 16 bits wide and point to bytes within the data space ...
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... PIC24FJ16MC101/102 FIGURE 4-3: DATA MEMORY MAP FOR PIC24FJ16MC101/102 DEVICES WITH 1 KB RAM MSB Address 0x0001 2 Kbyte SFR Space 0x07FF 0x0801 1 Kbyte SRAM Space 0x0BFF 0x0C01 0x1FFF 0x2001 0x8001 Optionally Mapped into Program Memory 0xFFFF DS39997B-page 30 LSB 16 bits Address MSb LSb 0x0000 ...
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TABLE 4-1: CPU CORE REGISTERS MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Addr WREG0 0000 WREG1 0002 WREG2 0004 WREG3 0006 WREG4 0008 WREG5 000A WREG6 000C WREG7 000E WREG8 0010 WREG9 0012 WREG10 0014 WREG11 0016 ...
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... TABLE 4-2: CHANGE NOTIFICATION REGISTER MAP FOR PIC24FJ16MC101 DEVICES SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr CNEN1 — 0060 CN14IE CN13IE CN12IE CNEN2 — — 0062 CN30IE CN29IE CNPU1 — 0068 CN14PUE CN13PUE CN12PUE CN11PUE CNPU2 — — 006A CN30PUE CN29PUE Legend unknown value on Reset, — ...
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TABLE 4-4: INTERRUPT CONTROLLER REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr — — — INTCON1 0080 NSTDIS INTCON2 0082 ALTIVT DISI — — IFS0 0084 — — AD1IF U1TXIF IFS1 0086 — — ...
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TABLE 4-5: TIMER REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON ...
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TABLE 4-8: 6-OUTPUT PWM1 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 P1TCON 01C0 PTEN — PTSIDL — P1TMR 01C2 PTDIR P1TPER 01C4 — P1SECMP 01C6 SEVTDIR PWM1CON1 01C8 — — — — PWM1CON2 01CA ...
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TABLE 4-10: UART1 REGISTER MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr U1MODE 0220 UARTEN — USIDL IREN U1STA 0222 UTXISEL1 UTXINV UTXISEL0 — U1TXREG 0224 — — — — U1RXREG 0226 — — — ...
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... TABLE 4-12: ADC1 REGISTER MAP FOR PIC24FJ16MC101 DEVICES File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 0300 ADC1BUF0 ADC1BUF1 0302 ADC1BUF2 0304 ADC1BUF3 0306 ADC1BUF4 0308 ADC1BUF5 030A ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 0312 ADC1BUFA 0314 ADC1BUFB 0316 ADC1BUFC 0318 ...
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TABLE 4-13: ADC1 REGISTER MAP FOR PIC24FJ16MC102 DEVICES File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 ADC1BUF0 0300 ADC1BUF1 0302 ADC1BUF2 0304 ADC1BUF3 0306 ADC1BUF4 0308 ADC1BUF5 030A ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 0312 ADC1BUFA ...
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TABLE 4-14: CTMU REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 CTMUCON1 033A CTMUEN — CTMUSIDL TGEN CTMUCON2 033C EDG1MOD EDG1POL EDG1SEL<3:0> CTMUICON 033E ITRIM<5:0> Legend unknown value on Reset, — = unimplemented, ...
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TABLE 4-17: COMPARATOR REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 CMSTAT 0650 CMSIDL — — CVRCON 0652 — — — CM1CON 0654 CON COE CPOL CM1MSKSRC 0656 — — — CM1MSKCON 0658 HLMS — ...
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... TABLE 4-19: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR PIC24FJ16MC101 DEVICES File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name RPOR0 06C0 — — — RPOR2 06C4 — — — — RPOR3 06C6 — — — RPOR4 06C8 — — — RPOR6 06CC — ...
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... ODCA 02C6 — — — — Legend unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-22: PORTB REGISTER MAP FOR PIC24FJ16MC101 DEVICES File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 TRISB 02C8 TRISB15 TRISB14 TRISB13 TRISB12 ...
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TABLE 4-24: SYSTEM CONTROL REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 RCON 0740 TRAPR IOPUWR — — OSCCON 0742 — COSC<2:0> CLKDIV 0744 ROI DOZE<2:0> OSCTUN 0748 — — — — Legend ...
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... PIC24FJ16MC101/102 4.2.5 SOFTWARE STACK In addition to its use as a working register, the W15 register in the PIC24FJ16MC101/102 devices is also used as a software Stack Pointer. The Stack Pointer always points to the first available free word and grows from lower to higher addresses. It pre-decrements for stack pops and post-increments for stack pushes, as ...
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... To use this data successfully, it must be accessed in a way that preserves the alignment of information in both spaces. Aside from normal execution, the PIC24FJ16MC101/ 102 architecture provides two methods by which program space can be accessed during operation: • Using table instructions to access individual bytes, or words, anywhere in the program space • ...
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... PIC24FJ16MC101/102 4.4.1 ADDRESSING PROGRAM SPACE Since the address ranges for the data and program spaces are 16 and 24 bits, respectively, a method is needed to create a 23-bit or 24-bit program address from 16-bit data registers. The solution depends on the interface method to be used. For table operations, the 8-bit Table Page register (TBLPAG) is used to define a 32K word region within the program space ...
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... Note 1: The Least Significant bit of program space addresses is always fixed as ‘0’ to maintain word alignment of data in the program and data spaces. 2: Table operations are not required to be word aligned. Table read operations are permitted in the configuration memory space. © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 Program Counter 0 23 bits 1/0 ...
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... PIC24FJ16MC101/102 4.4.2 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the lower word of any address within the program space without going through data space. The TBLRDH and TBLWTH instructions are the only method to read or write the upper 8 bits of a program space word as data ...
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... Microchip Technology Inc. PIC24FJ16MC101/102 24-bit program word are used to contain the data. The upper 8 bits of any program space location used as data should be programmed with ‘1111 ‘0000 0000’ to force a NOP. This prevents possible issues should the area of code ever be accidentally executed ...
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... PIC24FJ16MC101/102 NOTES: DS39997B-page 50 Preliminary © 2011 Microchip Technology Inc. ...
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... FLASH PROGRAM MEMORY Note 1: This data sheet summarizes the features of the PIC24FJ16MC101/102 family of devices not intended comprehensive reference source. To complement the information in this data sheet, refer to Section 4. “Program Memory” (DS39715) in the “PIC24F Family Reference Manual”, which is available from the Microchip web site (www ...
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... PIC24FJ16MC101/102 5.2 RTSP Operation The PIC24FJ16MC101/102 Flash program memory array is organized into rows of 64 instructions or 192 bytes. RTSP allows the user application to erase a page of memory, which consists of eight rows (512 instructions); and to program one word. shows typical erase and programming times. The 8- row erase pages are edge-aligned from the beginning of program memory, on boundaries of 1536 bytes ...
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... No operation 1100 = No operation 0011 = Memory word program operation 0010 = No operation 0001 = No operation 0000 = No operation Note 1: These bits can only be reset on POR. 2: All other combinations of NVMOP<3:0> are unimplemented. © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 (1) U-0 U-0 — — (1) U-0 R/W-0 — — ...
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... PIC24FJ16MC101/102 REGISTER 5-2: NVMKEY: NONVOLATILE MEMORY KEY REGISTER U-0 U-0 U-0 — — — bit 15 W-0 W-0 W-0 bit 7 Legend Settable only bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 NVMKEY< ...
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... RESETS Note 1: This data sheet summarizes the features of the PIC24FJ16MC101/102 family of devices not intended comprehensive reference source. To complement the information in this data sheet, refer to Section 7. “Reset” (DS39712) in the “PIC24F Reference Manual”, which is available from the Microchip (www.microchip.com important ...
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... PIC24FJ16MC101/102 REGISTER 6-1: RCON: RESET CONTROL REGISTER R/W-0 R/W-0 U-0 TRAPR IOPUWR — bit 15 R/W-0 R/W-0 R/W-0 EXTR SWR SWDTEN bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 TRAPR: Trap Reset Flag bit Trap Conflict Reset has occurred ...
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... System Reset The PIC24FJ16MC101/102 family of devices have two types of Reset: • Cold Reset • Warm Reset A cold Reset is the result of a POR or a BOR cold Reset, the FNOSC configuration bits in the FOSC device configuration register selects the device clock source. ...
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... PIC24FJ16MC101/102 FIGURE 6-2: SYSTEM RESET TIMING V POR POR 1 POR 2 BOR SYSRST Oscillator Clock FSCM Device Status 1. POR: A POR circuit holds the device in Reset when the power supply is turned on. The POR circuit is active until V V threshold and the delay T POR POR 2. BOR: The on-chip voltage regulator has a BOR circuit that keeps the device in Reset until V delay T has elapsed ...
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... SYSRST V dips before PWRT expires SYSRST © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 6.3 BOR and PWRT The on-chip regulator has a BOR circuit that resets the crosses the device when the V DD device operation. The BOR circuit keeps the device in Reset until V delay T has elapsed ...
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... PIC24FJ16MC101/102 6.4 External Reset (EXTR) The external Reset is generated by driving the MCLR pin low. The MCLR pin is a Schmitt trigger input with an additional glitch filter. Reset pulses that are longer than the minimum pulse width will generate a Reset. Refer to Section 26.0 “Electrical Characteristics” ...
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... IDLE (RCON<2>) BOR (RCON<1>) POR (RCON<0>) Note: All Reset flag bits can be set or cleared by user software. © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 6.9.3 SECURITY RESET If a Program Flow Change (PFC) or Vector Flow Change (VFC) targets a restricted location in a pro- tected segment (Boot and Secure Segment), that operation will cause a security Reset ...
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... PIC24FJ16MC101/102 NOTES: DS39997B-page 62 Preliminary © 2011 Microchip Technology Inc. ...
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... The Interrupt Controller reduces the numerous periph- eral interrupt request signals to a single interrupt request signal to the PIC24FJ16MC101/102 CPU. It has the following features: • eight processor exceptions and software traps • Seven user-selectable priority levels • ...
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... PIC24FJ16MC101/102 FIGURE 7-1: PIC24FJ16MC101/102 INTERRUPT VECTOR TABLE Reset – GOTO Instruction Reset – GOTO Address Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 Interrupt Vector 1 Interrupt Vector 52 ...
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... Microchip Technology Inc. PIC24FJ16MC101/102 AIVT Address Interrupt Source 0x000114 INT0 – External Interrupt 0 0x000116 IC1 – Input Capture 1 0x000118 OC1 – Output Compare 1 0x00011A T1 – Timer1 0x00011C Reserved 0x00011E IC2 – ...
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... Interrupt Control and Status Registers The PIC24FJ16MC101/102 devices implement a total of 22 registers for the interrupt controller: • INTCON1 • INTCON2 • IFSx • IECx • IPCx • INTTREG 7.3.1 INTCON1 AND INTCON2 Global interrupt control functions are controlled from INTCON1 and INTCON2. INTCON1 contains the Interrupt Nesting Disable bit (NSTDIS) as well as the control and status flags for the processor trap sources ...
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... CPU interrupt priority level is greater than CPU interrupt priority level less Note 1: For complete register details, see 2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level. © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 (1) U-0 U-0 — — (3) ...
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... PIC24FJ16MC101/102 REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 R/W-0 U-0 U-0 NSTDIS — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 NSTDIS: Interrupt Nesting Disable bit 1 = Interrupt nesting is disabled ...
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... INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 U-0 U-0 U-0 — — — U-0 ...
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... PIC24FJ16MC101/102 REGISTER 7-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 U-0 U-0 R/W-0 — — AD1IF bit 15 R/W-0 R/W-0 R/W-0 T2IF OC2IF IC2IF bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ bit 13 AD1IF: ADC1 Conversion Complete Interrupt Flag Status bit ...
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... IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 Preliminary DS39997B-page 71 ...
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... PIC24FJ16MC101/102 REGISTER 7-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1 U-0 U-0 R/W-0 — — INT2IF bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ bit 13 INT2IF: External Interrupt 2 Flag Status bit ...
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... Unimplemented: Read as ‘0’ bit 9 PWM1IF: PWM1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 8-0 Unimplemented: Read as ‘0’ © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 U-0 U-0 U-0 — — — U-0 U-0 U-0 — ...
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... PIC24FJ16MC101/102 REGISTER 7-9: IFS4: INTERRUPT FLAG STATUS REGISTER 4 U-0 U-0 R/W-0 — — CTMUIF bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ bit 13 CTMUIF: CTMU Interrupt Flag Status bit ...
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... T1IE: Timer1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 2 OC1IE: Output Compare Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 R/W-0 R/W-0 R/W-0 U1TXIE U1RXIE SPI1IE U-0 R/W-0 R/W-0 — ...
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... PIC24FJ16MC101/102 REGISTER 7-10: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED) bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DS39997B-page 76 Preliminary © 2011 Microchip Technology Inc. ...
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... MI2C1IE: I2C1 Master Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 SI2C1IE: I2C1 Slave Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 U-0 U-0 U-0 — — — R/W-0 ...
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... PIC24FJ16MC101/102 REGISTER 7-12: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2 U-0 U-0 U-0 — — — bit 15 U-0 U-0 R/W-0 — — IC3IE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-6 Unimplemented: Read as ‘0’ bit 5 IC3IE: Input Capture Channel 3 Interrupt Enable bit ...
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... U1EIE: UART1 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 FLTB1IE: PWM1 Fault B Interrupt Enable bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 U-0 U-0 U-0 — — — U-0 ...
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... PIC24FJ16MC101/102 REGISTER 7-15: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0 U-0 R/W-1 R/W-0 — T1IP<2:0> bit 15 U-0 R/W-1 R/W-0 — IC1IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 T1IP<2:0>: Timer1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • ...
Page 81
... IC2IP<2:0>: Input Capture Channel 2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 R/W-0 U-0 R/W-1 — R/W-0 U-0 U-0 — — ...
Page 82
... PIC24FJ16MC101/102 REGISTER 7-17: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2 U-0 R/W-1 R/W-0 — U1RXIP<2:0> bit 15 U-0 R/W-1 R/W-0 — SPI1EIP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 U1RXIP<2:0>: UART1 Receiver Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • ...
Page 83
... Unimplemented: Read as ‘0’ bit 2-0 U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 U-0 U-0 U-0 — — — R/W-0 U-0 R/W-1 — ...
Page 84
... PIC24FJ16MC101/102 REGISTER 7-19: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4 U-0 R/W-1 R/W-0 — CNIP<2:0> bit 15 U-0 R/W-1 R/W-0 — MI2C1IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 CNIP<2:0>: Change Notification Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • ...
Page 85
... INT2IP<2:0>: External Interrupt 2 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 U-0 U-0 U-0 — — — U-0 U-0 R/W-1 — ...
Page 86
... PIC24FJ16MC101/102 REGISTER 7-22: IPC9: INTERRUPT PRIORITY CONTROL REGISTER 9 U-0 U-0 U-0 — — — bit 15 U-0 R/W-1 R/W-0 — IC3IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 IC3IP<2:0>: External Interrupt 3 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • ...
Page 87
... RTCCIP<2:0>: RTCC Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7-0 Unimplemented: Read as ‘0’ © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 R/W-0 U-0 R/W-1 — U-0 U-0 U-0 — — ...
Page 88
... PIC24FJ16MC101/102 REGISTER 7-25: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16 U-0 U-0 U-0 — — — bit 15 U-0 R/W-1 R/W-0 — U1EIP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 U1EIP<2:0>: UART1 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • ...
Page 89
... CTMUIP<2:0>: CTMU Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 U-0 U-0 U-0 — — — R/W-0 U-0 U-0 — ...
Page 90
... PIC24FJ16MC101/102 REGISTER 7-27: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER U-0 U-0 U-0 — — — bit 15 U-0 R-0 R-0 — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-12 Unimplemented: Read as ‘0’ bit 11-8 ILR<3:0>: New CPU Interrupt Priority Level bits 1111 = CPU Interrupt Priority Level is 15 • ...
Page 91
... ISR is coded in assembly language, it must be terminated using a RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level. © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 7.4.3 TRAP SERVICE ROUTINE A Trap Service Routine (TSR) is coded like an ISR, except that the appropriate trap status flag in the INTCON1 register must be cleared to avoid re-entry into the TSR ...
Page 92
... PIC24FJ16MC101/102 NOTES: DS39997B-page 92 Preliminary © 2011 Microchip Technology Inc. ...
Page 93
... OSCILLATOR CONFIGURATION Note 1: This data sheet summarizes the features of the PIC24FJ16MC101/102 family of devices not intended comprehensive reference source. To complement the information in this data sheet, refer to Section 6. “Oscillator” (DS39700) in the “PIC24F Reference Manual”, which is available from the Microchip (www.microchip.com). ...
Page 94
... The output of the oscillator (or the output of the PLL if a PLL mode has been selected) F generate the device instruction clock (F peripheral clock time base (F operating speed of the device, and speeds MHz are supported by the PIC24FJ16MC101/102 architecture. Instruction execution speed or device operating frequency given by: ...
Page 95
... Primary Oscillator (EC) Fast RC Oscillator (FRC) with Divide-by-n and PLL (FRCPLL) Fast RC Oscillator (FRC) Note 1: OSC2 pin function is determined by the OSCIOFNC Configuration bit. 2: This is the default oscillator mode for an unprogrammed (erased) device. © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 EQUATION 8- Oscillator POSCMD<1:0> Source Internal ...
Page 96
... PIC24FJ16MC101/102 REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER U-0 R-0 R-0 — COSC<2:0> bit 15 R/W-0 R/W-0 R-0 CLKLOCK IOLOCK LOCK bit 7 Legend Value set from Configuration bits on POR R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ ...
Page 97
... Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 (1) (CONTINUED) Preliminary ...
Page 98
... PIC24FJ16MC101/102 REGISTER 8-2: CLKDIV: CLOCK DIVISOR REGISTER R/W-0 R/W-0 R/W-1 ROI DOZE<2:0> bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 ROI: Recover on Interrupt bit 1 = Interrupts will clear the DOZEN bit and the processor clock/peripheral clock ratio is set to 1:1 ...
Page 99
... Note 1: OSCTUN functionality has been provided to help customers compensate for temperature effects on the FRC frequency over a wide range of temperatures. The tuning step size is an approximation and is neither characterized nor tested. © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 U-0 U-0 U-0 — — ...
Page 100
... Applications are free to switch among any of the four clock sources (Primary, LP, FRC, and LPRC) under software control at any time. To limit the possible side effects of this flexibility, PIC24FJ16MC101/102 devices have a safeguard lock built into the switch process. Note: Primary Oscillator mode has three different submodes (MS, HS, and EC), which are determined by the POSCMD< ...
Page 101
... Clock Frequency and Clock Switching PIC24FJ16MC101/102 devices allow a wide range of clock frequencies to be selected under application control. If the system clock configuration is not locked, users can choose low-power or high-precision oscillators by simply changing the NOSC bits (OSCCON< ...
Page 102
... PIC24FJ16MC101/102 9.2.2 IDLE MODE The following occur in Idle mode: • The CPU stops executing instructions • The WDT is automatically cleared • The system clock source remains active. By default, all peripheral modules continue to operate normally from the system clock source, but can also be selectively disabled (see Section 9 ...
Page 103
... ADC1 module is enabled Note 1: PCFGx bits have no effect if the ADC module is disabled by setting this bit. When the bit is set, all port pins that have been multiplexed with ANx will be in Digital mode. © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 R/W-0 R/W-0 U-0 T2MD T1MD — ...
Page 104
... PIC24FJ16MC101/102 REGISTER 9-2: PMD2: PERIPHERAL MODULE DISABLE CONTROL REGISTER 2 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-11 Unimplemented: Read as ‘0’ bit 10 ...
Page 105
... Bit is set bit 15-4 Unimplemented: Read as ‘0’ bit 3 CTMUMD: CTMU Module Disable bit 1 = CTMU module is disabled 0 = CTMU module is enabled bit 2-0 Unimplemented: Read as ‘0’ © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 U-0 U-0 R/W-0 — — CMPMD U-0 U-0 U-0 — ...
Page 106
... PIC24FJ16MC101/102 NOTES: DS39997B-page 106 Preliminary © 2011 Microchip Technology Inc. ...
Page 107
... I/O PORTS Note 1: This data sheet summarizes the features of the PIC24FJ16MC101/102 family of devices not intended comprehensive reference source. To complement the information in this data sheet, refer to Section 12. “I/O Ports with Peripheral Pin Select (PPS)” (DS39711) in the “PIC24F Reference Manual”, which is available ...
Page 108
... DS39997B-page 108 10.3 Input Change Notification The input change notification function of the I/O ports allows the PIC24FJ16MC101/102 devices to generate interrupt requests to the processor in response to a change-of-state on selected input pins. This feature can detect input change-of-states even in Sleep mode, when the clocks are disabled. Depending on the device ...
Page 109
... The association of a peripheral to a peripheral select- able pin is handled in two different ways, depending on whether an input or output is being mapped. © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 10.4.2.1 Input Mapping The inputs of the peripheral pin select options are mapped on the basis of the peripheral. A control register associated with a peripheral dictates the pin it will be mapped to ...
Page 110
... PIC24FJ16MC101/102 TABLE 10-1: SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION) Input Name External Interrupt 1 External Interrupt 2 Timer2 External Clock Timer3 External Clock Input Capture 1 Input Capture 2 Input Capture 3 Output Compare Fault A UART1 Receive UART1 Clear To Send SPI1 Slave Select Input Note 1: Unless otherwise noted, all inputs use the Schmitt input buffers. ...
Page 111
... CHANGES Because peripheral remapping can be changed during run time, some restrictions on peripheral remapping are needed to prevent accidental configuration changes. PIC24FJ16MC101/102 devices include three features to prevent alterations to the peripheral map: • Control register lock sequence • Continuous state monitoring • Configuration bit pin select lock 10 ...
Page 112
... PIC24FJ16MC101/102 REGISTER 10-1: RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER 0 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 INT1R< ...
Page 113
... T2CKR<4:0>: Assign Timer2 External Clock (T2CK) to the corresponding RPn pin 11111 = Input tied V 01111 = Input tied to RP15 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 R/W-1 R/W-1 R/W-1 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS ...
Page 114
... PIC24FJ16MC101/102 REGISTER 10-4: RPINR7: PERIPHERAL PIN SELECT INPUT REGISTER 7 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 IC2R< ...
Page 115
... OCFAR<4:0>: Assign Output Capture A (OCFA) to the corresponding RPn pin 11111 = Input tied V 01111 = Input tied to RP15 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 U-0 U-0 — — R/W-1 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 116
... PIC24FJ16MC101/102 REGISTER 10-7: RPINR18: PERIPHERAL PIN SELECT INPUT REGISTER 18 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 U1CTSR< ...
Page 117
... SS1R<4:0>: Assign SPI1 Slave Select Input (SS1IN) to the corresponding RPn pin 11111 = Input tied V 01111 = Input tied to RP15 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 U-0 U-0 — — R/W-1 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 118
... PIC24FJ16MC101/102 REGISTER 10-9: RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTER 0 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP1R< ...
Page 119
... RP7R<4:0>: Peripheral Output Function is Assigned to RP7 Output Pin bits (see peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP6R<4:0>: Peripheral Output Function is Assigned to RP6 Output Pin bits (see peripheral function numbers) © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 R/W-0 R/W-0 R/W-0 RP5R<4:0> R/W-0 R/W-0 R/W-0 RP4R< ...
Page 120
... PIC24FJ16MC101/102 REGISTER 10-13: RPOR4: PERIPHERAL PIN SELECT OUTPUT REGISTER 4 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP9R< ...
Page 121
... RP15R<4:0>: Peripheral Output Function is Assigned to RP15 Output Pin bits (see peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP14R<4:0>: Peripheral Output Function is Assigned to RP14 Output Pin bits (see peripheral function numbers) © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 R/W-0 R/W-0 R/W-0 RP13R<4:0> R/W-0 R/W-0 R/W-0 RP12R< ...
Page 122
... PIC24FJ16MC101/102 NOTES: DS39997B-page 122 Preliminary © 2011 Microchip Technology Inc. ...
Page 123
... TIMER1 Note 1: This data sheet summarizes the features of the PIC24FJ16MC101/102 family of devices not intended comprehensive reference source. To complement the information in this data sheet, refer to Section 14. “Timers” (DS39704) in the “PIC24F Reference Manual”, which is available from the Microchip (www.microchip.com important ...
Page 124
... PIC24FJ16MC101/102 REGISTER 11-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 U-0 R/W-0 (1) TON — TSIDL bit 15 U-0 R/W-0 R/W-0 — TGATE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set (1) bit 15 TON: Timer1 On bit 1 = Starts 16-bit Timer1 0 = Stops 16-bit Timer1 bit 14 Unimplemented: Read as ‘ ...
Page 125
... TIMER2/3 FEATURE Note 1: This data sheet summarizes the features of the PIC24FJ16MC101/102 family of devices not intended comprehensive reference source. To complement the information in this data sheet, refer to Section 14. “Timers” (DS39704) in the “PIC24F Reference Manual”, which is available from the Microchip (www.microchip.com). ...
Page 126
... PIC24FJ16MC101/102 FIGURE 12-1: TIMER2/3 (32-BIT) BLOCK DIAGRAM T2CK TGATE 1 Set T3IF 0 (2) ADC Event Trigger Equal MSb Reset Read TMR2 Write TMR2 Data Bus<15:0> Note 1: The 32-bit timer control bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective to the T2CON register ...
Page 127
... T2CK TGATE 1 Set T2IF 0 Reset Equal FIGURE 12-3: TIMER3 (16-BIT) BLOCK DIAGRAM Gate Sync Prescaler F CY TCKPS<1:0> Prescaler Sync (/n) TxCK TCKPS<1:0> To CTMU Filter © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 Gate Sync TMR2 Comparator PR2 Falling Edge Detect 10 (/ TGATE TCS Preliminary TCKPS<1:0> ...
Page 128
... PIC24FJ16MC101/102 REGISTER 12-1: T2CON CONTROL REGISTER R/W-0 U-0 R/W-0 TON — TSIDL bit 15 U-0 R/W-0 R/W-0 — TGATE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 TON: Timer2 On bit When T32 = Starts 32-bit Timer2 Stops 32-bit Timer2/3 ...
Page 129
... When 32-bit timer operation is enabled (T32 = 1) in the Timer Control register (T2CON<3>), the TSIDL bit must be cleared to operate the 32-bit timer in Idle mode. 2: When the 32-bit timer operation is enabled (T32 = 1) in the Timer Control register (T2CON<3>), these bits have no effect. © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 U-0 U-0 (1) — — ...
Page 130
... PIC24FJ16MC101/102 NOTES: DS39997B-page 130 Preliminary © 2011 Microchip Technology Inc. ...
Page 131
... Section 4.0 “Memory Organization” this data sheet for device-specific register and bit information. The Input Capture module is useful in applications requiring frequency (period) and pulse measurement. The PIC24FJ16MC101/102 devices support up to eight input capture channels. FIGURE 13-1: INPUT CAPTURE BLOCK DIAGRAM Prescaler ...
Page 132
... PIC24FJ16MC101/102 13.1 Input Capture Registers REGISTER 13-1: ICxCON: INPUT CAPTURE x CONTROL REGISTER U-0 U-0 R/W-0 — — ICSIDL bit 15 R/W-0 R/W-0 R/W-0 ICTMR ICI<1:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ ...
Page 133
... OUTPUT COMPARE Note 1: This data sheet summarizes the features of the PIC24FJ16MC101/102 family of devices not intended comprehensive reference source. To complement the information in this data sheet, refer to Section 16. “Output Compare” (DS39706) of the “PIC24F Family Reference Manual”, which is available from the Microchip web site (www ...
Page 134
... PIC24FJ16MC101/102 14.1 Output Compare Modes Configure the Output Compare modes by setting the appropriate Output Compare Mode bits (OCM<2:0>) in the Output Compare Control register (OCxCON<2:0>). Table 14-1 lists the different bit settings for the Output Compare modes. Figure 14-2 illustrates the output compare operation for various modes ...
Page 135
... Compare event toggles OCx pin 010 = Initialize OCx pin high, compare event forces OCx pin low 001 = Initialize OCx pin low, compare event forces OCx pin high 000 = Output compare channel is disabled © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 U-0 U-0 U-0 — ...
Page 136
... PIC24FJ16MC101/102 NOTES: DS39997B-page 136 Preliminary © 2011 Microchip Technology Inc. ...
Page 137
... Refer to Section 4.0 “Memory Organization” this data sheet for device-specific register and bit information. The PIC24FJ16MC101/102 devices have a 6-channel Pulse-Width Modulation (PWM) module. The PWM module has the following features: • 16-bit resolution • On-the-fly PWM frequency changes • ...
Page 138
... PWM Time Base Note 1: The details of PWM Generator 1 and 2 are not shown for clarity PIC24FJ16MC101 (20-pin) devices, the FLTA1 pin is supported, but requires an external pull-down resistor for correct functionality PIC24FJ16MC102 (28-pin) devices, the FLTA1 and FLTB1 pins are supported and do not require an external pull-down resistor ...
Page 139
... PWM faults. Note: describes 15.3 Write-protected Registers On PIC24FJ16MC101/102 devices, write protection is implemented for the PWMxCON1, PxFLTACON and PxFLTBCON registers. The write protection feature prevents any inadvertent writes to these registers. The write protection feature can be controlled by the PWMLOCK configuration bit in the FOSCSEL configu- Internal Pull- ration register ...
Page 140
... PIC24FJ16MC101/102 EXAMPLE 15-1: ASSEMBLY CODE EXAMPLE FOR WRITE-PROTECTED REGISTER UNLOCK AND FAULT CLEARING SEQUENCE ; FLTA1 pin must be pulled high externally in order to clear and disable the fault ; Writing to P1FLTBCON register requires unlock sequence mov #0xabcd,w10 ; Load first unlock key to w10 register mov #0x4321,w11 ...
Page 141
... PWM time base operates in a Continuous Up/Down Count mode with interrupts for double PWM updates 10 = PWM time base operates in a Continuous Up/Down Count mode 01 = PWM time base operates in Single Pulse mode 00 = PWM time base operates in a Free-Running mode © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 U-0 U-0 U-0 — — ...
Page 142
... PIC24FJ16MC101/102 REGISTER 15-2: PxTMR: PWM TIMER COUNT VALUE REGISTER R-0 R/W-0 R/W-0 PTDIR bit 15 R/W-0 R/W-0 R/W-0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 PTDIR: PWM Time Base Count Direction Status bit (read-only PWM time base is counting down ...
Page 143
... A Special Event Trigger will occur when the PWM time base is counting up bit 14-0 SEVTCMP<14:0>: Special Event Compare Value bits Note 1: SEVTDIR is compared with PTDIR (P 2: PxSECMP<14:0> is compared with P © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 R/W-0 R/W-0 R/W-0 (2) SEVTCMP<14:8> R/W-0 R/W-0 R/W-0 (2) SEVTCMP< ...
Page 144
... PIC24FJ16MC101/102 REGISTER 15-5: PWMxCON1: PWM CONTROL REGISTER 1 U-0 U-0 U-0 — — — bit 15 U-0 R/W-0 R/W-0 — PEN3H PEN2H bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 PMOD3:PMOD1: PWM I/O Pair Mode bits ...
Page 145
... Output overrides via the PxOVDCON register occur on next T bit 0 UDIS: PWM Update Disable bit 1 = Updates from Duty Cycle and Period Buffer registers are disabled 0 = Updates from Duty Cycle and Period Buffer registers are enabled © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 U-0 R/W-0 R/W-0 — SEVOPS<3:0> ...
Page 146
... PIC24FJ16MC101/102 REGISTER 15-7: PxDTCON1: DEAD-TIME CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 DTBPS<1:0> bit 15 R/W-0 R/W-0 R/W-0 DTAPS<1:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 DTBPS<1:0>: Dead-Time Unit B Prescale Select bits 11 = Clock period for Dead-Time Unit ...
Page 147
... Dead time provided from Unit Dead time provided from Unit A bit 0 DTS1I: Dead-Time Select for PWM1 Signal Going Inactive bit 1 = Dead time provided from Unit Dead time provided from Unit A © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 U-0 U-0 U-0 — — — ...
Page 148
... PWMxH1/PWMxL1 pin pair is controlled by Fault Input PWMxH1/PWMxL1 pin pair is not controlled by Fault Input A Note 1: On PIC24FJ16MC101 (20-pin) devices, the FLTA1 pin is supported, but requires an external pull-down resistor for correct functionality PIC24FJ16MC102 (28-pin) devices, the FLTA1 and FLTB1 pins are supported and do not require an external pull-down resistor ...
Page 149
... PWMxH1/PWMxL1 pin pair is controlled by Fault Input PWMxH1/PWMxL1 pin pair is not controlled by Fault Input B Note 1: On PIC24FJ16MC101 (20-pin) devices, the FLTA1 pin is supported, but requires an external pull-down resistor for correct functionality PIC24FJ16MC102 (28-pin) devices, the FLTA1 and FLTB1 pins are supported and do not require an external pull-down resistor ...
Page 150
... PIC24FJ16MC101/102 REGISTER 15-11: PxOVDCON: OVERRIDE CONTROL REGISTER U-0 U-0 R/W-1 — — POVD3H bit 15 U-0 U-0 R/W-0 — — POUT3H bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 POVDxH<3:1>:POVDxL<3:1>: PWM Output Override bits ...
Page 151
... R/W-0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-0 PDC3<15:0>: PWM Duty Cycle 3 Value bits © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 R/W-0 R/W-0 R/W-0 PDC1<15:8> R/W-0 R/W-0 R/W-0 PDC1<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 152
... PIC24FJ16MC101/102 REGISTER 15-15: PWMxKEY: PWM KEY UNLOCK REGISTER R/W-0 R/W-0 R/W-0 bit 15 R/W-0 R/W-0 R/W-0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-0 PWMKEY<15:0>: PWM Key Unlock bits If the PWMLOCK Configuration bit is asserted (PWMLOCK = 1), the PWMxCON1, PxFLTACON and PxFLTBCON registers are writable only after the proper sequence is written to the PWMxKEY register ...
Page 153
... SERIAL PERIPHERAL INTERFACE (SPI) Note 1: This data sheet summarizes the features of the PIC24FJ16MC101/102 family of devices not intended comprehensive reference source. To complement the information in this data sheet, refer to Section 23. “Serial Peripheral Interface (SPI)” (DS39699) in the “PIC24F Family Manual”, which is available from the ...
Page 154
... PIC24FJ16MC101/102 REGISTER 16-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER R/W-0 U-0 R/W-0 SPIEN — SPISIDL bit 15 U-0 R/C-0 U-0 — SPIROV — bit 7 Legend Clearable bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 SPIEN: SPIx Enable bit ...
Page 155
... The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1). 2: This bit must be cleared when FRMEN = not set both Primary and Secondary prescalers to a value of 1:1. © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 R/W-0 R/W-0 R/W-0 DISSCK DISSDO MODE16 ...
Page 156
... PIC24FJ16MC101/102 REGISTER 16-2: SPI CON1: SPIx CONTROL REGISTER 1 (CONTINUED) X bit 4-2 SPRE<2:0>: Secondary Prescale bits (Master mode) 111 = Secondary prescale 1:1 110 = Secondary prescale 2:1 • • • 000 = Secondary prescale 8:1 bit 1-0 PPRE<1:0>: Primary Prescale bits (Master mode Primary prescale 1:1 ...
Page 157
... FRMDLY: Frame Sync Pulse Edge Select bit 1 = Frame sync pulse coincides with first bit clock 0 = Frame sync pulse precedes first bit clock bit 0 Unimplemented: This bit must not be set to ‘1’ by the user application. © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 U-0 U-0 U-0 — — ...
Page 158
... PIC24FJ16MC101/102 NOTES: DS39997B-page 158 Preliminary © 2011 Microchip Technology Inc. ...
Page 159
... INTER-INTEGRATED CIRCUIT™ C™) Note 1: This data sheet summarizes the features of the PIC24FJ16MC101/102 family of devices not intended comprehensive reference source. To complement the information in this data sheet, refer to Section 24. “Inter-Inte- 2 grated Circuit™ (I C™)” (DS39702) in the “PIC24F Family Reference Manual”, which is available from the Microchip web site (www ...
Page 160
... PIC24FJ16MC101/102 2 FIGURE 17-1: I C™ BLOCK DIAGRAM ( Shift SCLx Clock SDAx Shift Clock BRG Down Counter DS39997B-page 160 = 1) X I2CxRCV I2CxRSR LSb Address Match Match Detect I2CxADD Start and Stop Bit Detect Start and Stop Bit Generation Collision Detect Acknowledge Generation ...
Page 161
... General call address disabled bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I Used in conjunction with SCLREL bit Enable software or receive clock stretching 0 = Disable software or receive clock stretching © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 R/W-1 HC R/W-0 R/W-0 SCLREL IPMIEN A10M ...
Page 162
... PIC24FJ16MC101/102 REGISTER 17-1: I2CxCON: I2Cx CONTROL REGISTER (CONTINUED) bit 5 ACKDT: Acknowledge Data bit (when operating as I Value that will be transmitted when the software initiates an Acknowledge sequence Send NACK during Acknowledge 0 = Send ACK during Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit 2 (when operating Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit ...
Page 163
... P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 U-0 U-0 — — R/C-0 HSC R/C-0 HSC ...
Page 164
... PIC24FJ16MC101/102 REGISTER 17-2: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED) bit 3 S: Start bit 1 = Indicates that a Start (or Repeated Start) bit has been detected last 0 = Start bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. bit 2 R_W: Read/Write Information bit (when operating Read – ...
Page 165
... AMSKx: Mask for Address bit x Select bit 1 = Enable masking for bit x of incoming message address; bit match not required in this position 0 = Disable masking for bit x; bit match required in this position © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 U-0 U-0 U-0 — ...
Page 166
... PIC24FJ16MC101/102 NOTES: DS39997B-page 166 Preliminary © 2011 Microchip Technology Inc. ...
Page 167
... The Universal Asynchronous Receiver Transmitter (UART) module is one of the serial I/O modules available in the PIC24FJ16MC101/102 device family. The UART is a full-duplex asynchronous system that can communicate with peripheral devices, such as personal computers, LIN 2.0, and RS-232, and RS-485 interfaces ...
Page 168
... PIC24FJ16MC101/102 REGISTER 18-1: UxMODE: UART R/W-0 U-0 R/W-0 (1) UARTEN — USIDL bit 15 R/W-0 HC R/W-0 R/W-0 HC WAKE LPBACK ABAUD bit 7 Legend Hardware cleared R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 UARTEN: UARTx Enable bit 1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0> ...
Page 169
... Refer to Section 21. “UART” (DS39708) in the “PIC24F Family Reference Manual” for information on enabling the UART module for receive or transmit operation. 2: This feature is only available for the 16x BRG mode (BRGH = 0). © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 MODE REGISTER (CONTINUED) x Preliminary DS39997B-page 169 ...
Page 170
... PIC24FJ16MC101/102 REGISTER 18-2: U STA: UART x R/W-0 R/W-0 R/W-0 UTXISEL1 UTXINV UTXISEL0 bit 15 R/W-0 R/W-0 R/W-0 URXISEL<1:0> ADDEN bit 7 Legend Hardware cleared R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15,13 UTXISEL<1:0>: Transmission Interrupt Mode Selection bits 11 = Reserved; do not use ...
Page 171
... Receive buffer has data, at least one more character can be read 0 = Receive buffer is empty Note 1: Refer to Section 21. “UART” (DS39708) in the “PIC24F Family Reference Manual” for information on enabling the UART module for transmit operation. © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 STATUS AND CONTROL REGISTER (CONTINUED) x Preliminary DS39997B-page 171 ...
Page 172
... PIC24FJ16MC101/102 NOTES: DS39997B-page 172 Preliminary © 2011 Microchip Technology Inc. ...
Page 173
... Refer to Section 4.0 “Memory Organization” this data sheet for device-specific register and bit information. The PIC24FJ16MC101/102 devices have up to six ADC module input channels. 19.1 Key Features The 10-bit ADC configuration has the following key features: • ...
Page 174
... PIC24FJ16MC101/102 FIGURE 19-1: ADC1 BLOCK DIAGRAM FOR PIC24FJ16MC101 DEVICES (1) CTMU (2) Open AN0 AN3 Channel Scan CH0SB<4:0> CH0SA<4:0> CH0 CSCNA AN1 AVss CH0NA CH0NB AN0 AN3 CH123SA CH123SB CH1 AVss CH123NA CH123NB AN1 CH123SA CH123SB CH2 AVss CH123NA CH123NB AN2 CH123SA CH123SB ...
Page 175
... CH2 AVss CH123NA CH123NB AN2 AN5 CH123SA CH123SB CH3 AVss CH123NA CH123NB Alternate Input Selection Note 1: Internally connected to CTMU module. 2: This selection is only used with CTMU capacitive and time measurement. © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 (1) CTMUI Preliminary AV AV ...
Page 176
... PIC24FJ16MC101/102 FIGURE 19-3: ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM ADC Internal (1) RC Clock T CY OSC ( Note 1: See the ADC specifications in DS39997B-page 176 ADxCON3<5:0> 6 ADC Conversion Clock Multiplier 5,..., 64 Section 26.0 “Electrical Characteristics” Preliminary ADxCON3<15> for the exact RC clock value. © 2011 Microchip Technology Inc. ...
Page 177
... If ASAM = 0, software can write ‘1’ to begin sampling. Automatically set by hardware if ASAM = 1. If SSRC = 000, software can write ‘0’ to end sampling and start conversion. If SSRC ≠ 000, automatically cleared by hardware to end sampling and start conversion. © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 U-0 U-0 — ...
Page 178
... PIC24FJ16MC101/102 REGISTER 19-1: AD1CON1: ADC1 CONTROL REGISTER 1 (CONTINUED) bit 0 DONE: ADC Conversion Status bit 1 = ADC conversion cycle is completed 0 = ADC conversion not started or in progress Automatically set by hardware when ADC conversion is complete. Software can write ‘0’ to clear DONE status (software not allowed to write ‘1’). Clearing this bit will NOT affect any operation in progress ...
Page 179
... Always starts filling buffer from the beginning bit 0 ALTS: Alternate Input Sample Mode Select bit 1 = Uses channel input selects for Sample A on first sample and Sample B on next sample 0 = Always uses channel input selects for Sample A © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 U-0 U-0 R/W-0 — — ...
Page 180
... PIC24FJ16MC101/102 REGISTER 19-3: AD1CON3: ADC1 CONTROL REGISTER 3 R/W-0 U-0 U-0 ADRC — — bit 15 R/W-0 R/W-0 R/W-0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 ADRC: ADC Conversion Clock Source bit 1 = ADC internal RC clock 0 = Clock derived from system clock bit 14-13 Unimplemented: Read as ‘ ...
Page 181
... CH1, CH2, CH3 negative input is AVss bit 8 CH123SB: Channel Positive Input Select for Sample B bit PIC24FJ16MC101 devices only CH1 positive input is AN3, CH2 and CH3 positive inputs are not connected 0 = CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2 ...
Page 182
... Unimplemented: Read as ‘0’ bit 4-0 CH0SA<4:0>: Channel 0 Positive Input Select for Sample A bits PIC24FJ16MC101 devices only: 01110 = No channels connected; all inputs are floating (used for CTMU) 01101 = Channel 0 positive input is connected to CTMU temperature sensor 00011 = Channel 0 positive input is AN3 ...
Page 183
... On devices without 6 analog inputs, all AD1CSSL bits can be selected by user application. However, inputs selected for scan without a corresponding input on device converts V 2: CSSx = ANx, where through 5. 3: CTMU temperature sensor input cannot be scanned. © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 U-0 U-0 U-0 — — — ...
Page 184
... PIC24FJ16MC101/102 REGISTER 19-7: AD1PCFGL: ADC1 PORT CONFIGURATION REGISTER LOW U-0 U-0 U-0 — — — bit 15 U-0 U-0 R/W-0 — — PCFG5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 PCFG< ...
Page 185
... COMPARATOR MODULE Note 1: This data sheet summarizes the features of the PIC24FJ16MC101/102 families of devices not intended comprehensive reference source. To complement the information in this data sheet, refer to Section 48. “Comparator with Blanking” (DS39741) “PIC24F Family Reference Manual”, which is available from the Microchip website (www ...
Page 186
... PIC24FJ16MC101/102 FIGURE 20-1: COMPARATOR I/O OPERATING MODES INTREF C1INB MUX C1INC C1IND REFIN MUX C1INA INTREF C2INB MUX C2INC C2IND REFIN MUX C2INA INTREF C3INB MUX C3INC C3IND REFIN MUX C3INA BGSEL<1:0> (1) 1.2V Note 1: This reference voltage is generated internally on the device. Refer to the specified voltage range ...
Page 187
... USER PROGRAMMABLE BLANKING FUNCTION BLOCK DIAGRAM SELSRCA<3:0> MAI Blanking Signals SELSRCB<3:0> MAI MBI MCI Blanking MAI MBI Signals MBI MCI SELSRCC<3:0> Blanking MCI Signals © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 CVRCON<3:0> CV RSRC CVRCON<CVROE> Note 1: This pin Analog Comparator Output ANDI AND ...
Page 188
... PIC24FJ16MC101/102 FIGURE 20-4: DIGITAL FILTER INTERCONNECT BLOCK DIAGRAM Timer2 Timer3 PWM Special Event Trigger F OSC F CY From Blanking Logic DS39997B-page 188 ÷ CFDIV CFSEL<2:0> Digital Filter Preliminary CFLTREN C OUT X © 2011 Microchip Technology Inc. ...
Page 189
... When CPOL = > < When CPOL = < > © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 U-0 U-0 R-0 — — C3EVT U-0 U-0 R-0 — — C3OUT U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R-0 R-0 C2EVT C1EVT bit 8 R-0 R-0 ...
Page 190
... PIC24FJ16MC101/102 REGISTER 20-2: CMxCON: COMPARATOR CONTROL REGISTER R/W-0 R/W-0 R/W-0 CON COE CPOL bit 15 R/W-0 R/W-0 U-0 EVPOL<1:0> — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 CON: Comparator Enable bit 1 = Comparator is enabled 0 = Comparator is disabled bit 14 ...
Page 191
... Unimplemented: Read as ‘0’ bit 1-0 CCH<1:0>: Comparator Channel Select bits input of comparator connects to INTREF input of comparator connects input of comparator connects input of comparator connects © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 + input) IN voltage REFIN IND pin X INC pin X INB pin X Preliminary DS39997B-page 191 ...
Page 192
... PIC24FJ16MC101/102 REGISTER 20-3: CMxMSKSRC: COMPARATOR MASK SOURCE SELECT CONTROL REGISTER U-0 U-0 U-0 — — — bit 15 R/W-0 R/W-0 R/W-0 SELSRCB<3:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-12 Unimplemented: Read as ‘0’ bit 11-8 SELSRCC< ...
Page 193
... Reserved 1110 = Reserved 1101 = Reserved 1100 = Reserved 1011 = Reserved 1010 = Reserved 1001 = Reserved 1000 = Reserved 0111 = Reserved 0110 = Reserved 0101 = PWM1H3 0100 = PWM1L3 0011 = PWM1H2 0010 = PWM1L2 0001 = PWM1H1 0000 = PWM1L1 © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 Preliminary DS39997B-page 193 ...
Page 194
... PIC24FJ16MC101/102 REGISTER 20-4: CMxMSKCON: COMPARATOR MASK GATING CONTROL REGISTER R/W-0 U-0 R/W-0 HLMS — OCEN bit 15 R/W-0 R/W-0 R/W-0 NAGS PAGS ACEN bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 HLMS: High or Low Level Masking Select bits 1 = The masking (blanking) function will prevent any asserted (‘ ...
Page 195
... AAEN: AND Gate A1 A Input Enable bit 1 = MAI is connected to AND gate 0 = MAI is not connected to AND gate bit 0 AANEN: AND Gate A1 A Input Inverted Enable bit 1 = Inverted MAI is connected to AND gate 0 = Inverted MAI is not connected to AND gate © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 Preliminary DS39997B-page 195 ...
Page 196
... PIC24FJ16MC101/102 REGISTER 20-5: CMxFLTR: COMPARATOR FILTER CONTROL REGISTER U-0 U-0 U-0 — — — bit 15 U-0 R/W-0 R/W-0 — CFSEL<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 CFSEL<2:0>: Comparator Filter Input Clock Select bits ...
Page 197
... REFIN RSRC Note 1: CVROE overrides the TRIS bit setting. 2: This reference voltage is generated internally on the device. Refer to Characteristics” for the specified voltage range. © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 U-0 U-0 — — VREFSEL U-0 R/W-0 — Unimplemented bit, read as ‘0’ ...
Page 198
... PIC24FJ16MC101/102 NOTES: DS39997B-page 198 Preliminary © 2011 Microchip Technology Inc. ...
Page 199
... REAL-TIME CLOCK AND CALENDAR (RTCC) Note 1: This data sheet summarizes the features of the PIC24FJ16MC101/102 family of devices not intended comprehensive reference source. To complement the information in this data sheet, refer to Section 29. “Real-Time Clock and Calendar (DS39696) in the “PIC24F Reference Manual”, which is available on ...
Page 200
... PIC24FJ16MC101/102 21.1 RTCC Module Registers The RTCC module registers are organized into three categories: • RTCC Control Registers • RTCC Value Registers • Alarm Value Registers 21.1.1 REGISTER MAPPING To limit the register interface, the RTCC Timer and Alarm Time registers are accessed corresponding register pointers ...