PXF4333V11 INFINEON [Infineon Technologies AG], PXF4333V11 Datasheet - Page 294
![no-image](/images/no-image-200.jpg)
PXF4333V11
Manufacturer Part Number
PXF4333V11
Description
ABM 3G ATM Buf fer Manager
Manufacturer
INFINEON [Infineon Technologies AG]
Datasheet
1.PXF4333V11.pdf
(361 pages)
- Current page: 294 of 361
- Download datasheet (6Mb)
Register 98 EXTRAMC
CPU Accessibility:
Reset Value:
Offset Address:
Typical Usage:
Bit
Bit
CSRDW
CSRDR
CSRUW
CSRUR
CPRW
CPRR
Data Sheet
Setting a command bit starts the Read or Write procedure from/to the selected external
RAM. The corresponding bit is automatically cleared after completion of the Read/Write
procedure.
The address to be read or to be written is provided in registers
EXTRAMA1. The 32-bit wide data is transferred via registers
EXTRAMD1.
Note: Access to external RAM is only allowed before first cell flow.
15
Unused(1:0)
7
External RAM Test Command Register
14
Cell Storage RAM downstream write
Cell Storage RAM downstream read
Cell Storage RAM upstream write
Cell Storage RAM upstream read
Cell Pointer RAM write
Cell Pointer RAM read
6
Read/Write
0000
EXTRAMA0 E0
Written and Read by CPU
H
CSRDW CSRDR CSRUW CSRUR
13
5
H
Unused(13:2)
12
4
294
11
3
10
2
EXTRAMD0
EXTRAMA0
Register Description
CPRW
PXF 4333 V1.1
9
1
and
and
2001-12-17
ABM-3G
CPRR
8
0
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