ADP1046-100-EVALZ AD [Analog Devices], ADP1046-100-EVALZ Datasheet - Page 80

• Manufacturer Part Number: ADP1046-100-EVALZ
• Description: Digital Controller for Isolated
• Manufacturer: AD [Analog Devices]

ADP1046
Table 112. Register 0x70—Dead Time Configuration
Bits
[7:6]
[5:3]
[2:0]
SOFT START FILTER PROGRAMMING REGISTERS
Table 113. Register 0x71—Soft Start Digital Filter LF Gain Setting
Bits
[7:0]
Table 114. Register 0x72—Soft Start Digital Filter Zero Setting
Bits
[7:0]
Table 115. Register 0x73—Soft Start Digital Filter Pole Setting
Bits
[7:0]
Table 116. Register 0x74—Soft Start Digital Filter HF Gain Setting
Bits
[7:0]
Pole location
Bit Name
Averaging period
Update rate
Multiplier
Bit Name
LF gain setting
Bit Name
Zero setting
Bit Name
Bit Name
HF gain setting
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
These bits specify the averaging period for the CS1 current used to set the adaptive dead time. It is
recommended that the averaging time be set to a value much greater than any transient condition.
Bit 7
0
0
1
1
The ADT algorithm adjusts the dead time in steps of 5 ns. These bits are used to program the
number of PWM switching cycles between each step. The number is calculated as 2
N is the 3-bit value specified by these bits. If N = 6 (110), each PWM edge is adjusted by 5 ns every
2
These bits specify the programming step for Register 0x69 to Register 0x6F, Bits[6:4] and Bits[2:0].
Bit 2
0
0
0
0
1
1
1
1
Description
This register determines the low frequency gain of the loop response. Programmable over a 20 dB
range. Each LSB corresponds to a 0.3 dB increase. See Figure 57.
Description
This register determines the position of the final zero. See Figure 57.
Description
This register determines the position of the final pole. See Figure 57.
Description
This register determines the high frequency gain of the loop response. Programmable over a 20 dB
range. Each LSB corresponds to a 0.3 dB increase. See Figure 57.
6
+ 1 = 65 switching cycles.
Bit 6
0
1
0
1
Bit 1
0
0
1
1
0
0
1
1
Rev. 0 | Page 80 of 96
Averaging Period
2.5 ms
1.2 ms
600 μs
Reserved
Bit 0
0
1
0
1
0
1
0
1
Multiplier
5
10
15
20
25
30
35
40
Data Sheet
N
+ 1 where