ADP1046-100-EVALZ AD [Analog Devices], ADP1046-100-EVALZ Datasheet - Page 70

• Manufacturer Part Number: ADP1046-100-EVALZ
• Description: Digital Controller for Isolated
• Manufacturer: AD [Analog Devices]

ADP1046
Table 78. Register 0x4E—OUTD Rising Edge Setting (OUTD Pin)
Bits
[7:4]
3
2
1
0
Table 79. Register 0x4F—OUTD Falling Edge Timing (OUTD Pin)
Bits
[7:0]
Table 80. Register 0x50—OUTD Falling Edge Setting (OUTD Pin)
Bits
[7:4]
3
2
[1:0]
Table 81. Register 0x51—SR1 Rising Edge Timing (SR1 Pin)
Bits
[7:0]
Bit Name
t
Modulate enable
t
Reserved
Volt-second balance
source selection
Bit Name
t
Bit Name
t
Modulate enable
t
Reserved
Bit Name
t
7
7
8
8
8
9
sign
sign
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
These bits contain the four LSBs of the 12-bit t
bits of Register 0x4D, which contains the eight MSBs of the t
5 ns resolution. The entire switching period is divided into 40 ns time steps. If the t_rise and
t_fall of a PWM edge occur within the same 40 ns time step, the PWM output is 0 V. If the t_rise
and t_fall occur in different 40 ns time steps, the PWM output is set to the programmed value.
The absolute maximum pulse width is t
1 = PWM modulation acts on the t
0 = no PWM modulation of the t
1 = negative sign. Increase of PWM modulation moves t
0 = positive sign. Increase of PWM modulation moves t
Reserved.
If this bit is set to 1, the OUTD rising edge is selected as the start of the integration period for
volt-second balance.
Description
This register contains the eight MSBs of the 12-bit t
four bits of Register 0x50, which contains the four LSBs of the t
5 ns resolution. The entire switching period is divided into 40 ns time steps. If the t_rise and
t_fall of a PWM edge occur within the same 40 ns time step, the PWM output is 0 V. If the t_rise
and t_fall occur in different 40 ns time steps, the PWM output is set to the programmed value.
The absolute maximum pulse width is t
Description
These bits contain the four LSBs of the 12-bit t
bits of Register 0x4F, which contains the eight MSBs of the t
5 ns resolution. The entire switching period is divided into 40 ns time steps. If the t_rise and
t_fall of a PWM edge occur within the same 40 ns time step, the PWM output is 0 V. If the t_rise
and t_fall occur in different 40 ns time steps, the PWM output is set to the programmed value.
The absolute maximum pulse width is t
1 = PWM modulation acts on the t
0 = no PWM modulation of the t
1 = negative sign. Increase of PWM modulation moves t
0 = positive sign. Increase of PWM modulation moves t
Reserved.
Description
This register contains the eight MSBs of the 12-bit t
four bits of Register 0x52, which contains the four LSBs of the t
5 ns resolution. The entire switching period is divided into 40 ns time steps. If the t_rise and
t_fall of a PWM edge occur within the same 40 ns time step, the PWM output is 0 V. If the t_rise
and t_fall occur in different 40 ns time steps, the PWM output is set to the programmed value.
The absolute maximum pulse width is t
not be set between 80 ns and 115 ns when using the SR soft start.
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7
8
edge.
edge.
7
8
edge.
edge.
PERIOD
PERIOD
PERIOD
PERIOD
− 5 ns.
− 5 ns.
− 5 ns.
− 5 ns. It is recommended that the SR1 rising edge
7
8
time. This value is always used with the eight
time. This value is always used with the eight
8
9
time. This value is always used with the top
time. This value is always used with the top
7
8
7
8
left.
left.
right.
right.
8
7
time. Each LSB corresponds to
time. Each LSB corresponds to
8
9
time. Each LSB corresponds to
time. Each LSB corresponds to
Data Sheet