ADP1046-100-EVALZ AD [Analog Devices], ADP1046-100-EVALZ Datasheet - Page 57

• Manufacturer Part Number: ADP1046-100-EVALZ
• Description: Digital Controller for Isolated
• Manufacturer: AD [Analog Devices]

Data Sheet
Bits
2
[1:0]
Table 41. Register 0x29—Share Bus Bandwidth
Bits
[7:5]
4
3
[2:0]
Table 42. Register 0x2A—Share Bus Setting
Bits
[7:4]
[3:0]
Table 43. Register 0x2B—Temperature Gain Trim
Bits
7
[6:0]
Table 44. Register 0x2C—PSON/Soft Start
Bits
[7:6]
5
[4:3]
Bit Name
Volt-second balance
modulation
Volt-second balance
gain setting
Bit Name
Reserved
Bit stream
Current share select
Share bus bandwidth
Bit Name
Number of bits
dropped by master
Bit difference between
master and slave
Bit Name
Gain polarity
Gain trim
Bit Name
PS_ON setting
PS_ON
PS_ON delay
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
These bits determine which signal is used by the
Bit 7
0
0
1
1
Software PS_ON bit.
0 = power supply off.
1 = power supply on.
These bits set the time from when the PS_ON control signal is set to when the soft start begins.
Bit 4
0
0
1
1
Description
These bits determine how much a master device reduces its output voltage to maintain
current sharing.
These bits determine how closely a slave tries to match the current of the master device. The
higher the setting, the larger the voltage difference that satisfies the current sharing criteria.
Description
1 = negative gain is introduced.
0 = positive gain is introduced.
This register calibrates the RTD ADC gain. It calibrates for errors in the ADC.
Description
This bit specifies the maximum amount of modulation from volt-second balance.
0 = ±80 ns maximum.
1 = ±160 ns maximum.
These bits set the gain of the volt-second balance circuit. The gain can be changed by a factor of
64. When these bits are set to 00, it takes approximately 700 ms to achieve volt-second balance.
When these bits are set to 11, it takes approximately 10 ms to achieve volt-second balance.
Bit 1
0
0
1
1
Description
Reserved.
1 = the current sense ADC reading is output on the SHAREo pin. This bit stream can be used for
analog current sharing.
0 = the digital share bus signal is output on the SHAREo pin. This signal can be used for digital
current sharing.
1 = CS1 reading used for current share.
0 = CS2 reading used for current share.
These bits determine the amount of bandwidth dedicated to the share bus. The value 000 is
the lowest possible bandwidth, and the value 111 is the highest possible bandwidth.
Bit 6
0
1
0
1
Bit 3
0
1
0
1
PS_ON Setting
The
Hardware PSON pin is used to enable or disable the power supply.
Software PS_ON bit (Bit 5) is used to enable or disable the power supply.
Both the software PS_ON bit and the hardware PSON pin must be enabled
before the
Typical Delay (sec)
0
0.5
1
2
Rev. 0 | Page 57 of 96
Bit 0
0
1
0
1
ADP1046
ADP1046
is always on.
Volt-Second Balance Gain
1
4
16
64
is enabled.
ADP1046
as the PS_ON control.
ADP1046