ADP1046-100-EVALZ AD [Analog Devices], ADP1046-100-EVALZ Datasheet - Page 64

• Manufacturer Part Number: ADP1046-100-EVALZ
• Description: Digital Controller for Isolated
• Manufacturer: AD [Analog Devices]

ADP1046
PWM AND SYNCHRONOUS RECTIFIER TIMING REGISTERS
Figure 56 and Table 63 to Table 93 describe the implementation and programming of the seven PWM signals that are output from the
ADP1046. In general, it is recommended that t
Table 63. Register 0x3F—OUTAUX Switching Frequency Setting
Bits
7
6
[5:0]
Bit Name
Pulse skipping
Pulse skipping zero
PWM
Switching frequency
R/W
R/W
R/W
R/W
SYNC RECT 1 (SR1)
SYNC RECT 2 (SR2)
PWM5 (OUTAUX)
PWM1 (OUTA)
PWM2 (OUTB)
PWM3 (OUTC)
PWM4 (OUTD)
This register sets the switching frequency of the OUTAUX signal.
Description
Setting this bit enables pulse skipping mode. If the
the modulation low limit, pulse skipping is enabled.
0 = pulse skipping drives all modulated PWM outputs to 0 V.
1 = sets all modulated edges to t = 0 (the crossing rule set in Register 0x52[0] applies).
Bit 5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
be set to 0 and that t
Bit 4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
Figure 56. PWM Timing Diagram
t
t
t
12
13
3
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t
t
t
t
t
11
14
4
t
1
6
t
2
5
t
t
10
7
t
PERIOD
t
t
8
9
Bit 3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
be set as the reference point for the other signals.
Bit 2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
t
PERIOD
Bit 1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
ADP1046
Bit 0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
requires a duty cycle lower than
Frequency (kHz)
48.83
50.40
52.08
53.88
55.80
57.87
60.1
62.5
65.1
67.93
71.02
74.4
78.13
82.24
86.81
91.91
97.66
100.81
104.17
Data Sheet