PSD4235G2-12UIT STMICROELECTRONICS [STMicroelectronics], PSD4235G2-12UIT Datasheet - Page 93

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PSD4235G2-12UIT

Manufacturer Part Number
PSD4235G2-12UIT
Description
Flash in-system programmable (ISP) peripherals for 16-bit MCUs (3.3 V supply)
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
PSD4235G2V
20.7
Input control signals
The PSD provides the option to turn off the address input (A7-A0) and input control signals
(CNTL0, CNTL1, CNTL2, Address Strobe (ALE/AS, PD0) and Write Enable high-byte
(WRH/DBE, PD3)) to the PLD to save AC power consumption. These signals are inputs to
the PLD AND Array. During Power-down mode, or, if any of them are not being used as part
of the PLD logic equation, these control signals should be disabled to save AC power. They
are disconnected from the PLD AND Array by setting bits 0, 2, 3, 4, 5 and 6 to a ’1’ in
PMMR2.
Table 49.
APD Enable
bit
0
1
1
1
APD counter operation
ALE PD
polarity
X
X
1
0
ALE level
Pulsing
X
1
0
Counting (Generates PDN after 15 clocks)
Counting (Generates PDN after 15 clocks)
APD counter
Not counting
Not counting
Power management
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