PSD4235G2-12UIT STMICROELECTRONICS [STMicroelectronics], PSD4235G2-12UIT Datasheet - Page 27

• Manufacturer Part Number: PSD4235G2-12UIT
• Description: Flash in-system programmable (ISP) peripherals for 16-bit MCUs (3.3 V supply)
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

PSD4235G2V
5.12
5.13
5.14
5.15
Flash Boot Protection register
Table 19.
Sec<i>_Prot:
Security_Bit:
JTAG Enable register
Table 20.
JTAGEnable:
Page register
This register configures the page input to PLD.
Default value is PGR7-PGR0=0.
Table 21.
PMMR0 register
The bits of this register are cleared to zero following Power-up. Subsequent Reset (RESET)
pulses do not clear the registers.
Table 22.
Bit 7
Security_
Bit
Bit 7
not used
Bit 7
PGR 7
Bit 7
not used
(set to ’0’)
1: Secondary Flash memory Sector <i> is write protected.
0: Secondary Flash memory Sector <i> is not write protected.
0: Security bit in device has not been set.
1: Security bit in device has been set.
1: JTAG Port is enabled.
0: JTAG Port is disabled.
Bit 6
not used
(set to ’0’)
Bit 6
not used
Bit 6
not used
Bit 6
PGR 6
Flash Boot Protection register
JTAG Enable register
Page register
PMMR0 register
Bit 5
not used
Bit 5
not used
Bit 5
PGR 5
Bit 5
PLD
MCells
CLK
Bit 4
Bit 4
not used
Bit 4
not used
Bit 4
PGR 4
PLD
Array CLK
Bit 3
PLD
Turbo
Bit 3
Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot
Bit 3
not used
Bit 3
PGR 3
Bit 2
not used
(set to ’0’)
Bit 2
Bit 2
not used
Bit 2
PGR 2
Register bit definition
Bit 1
APD
Enable
Bit 1
Bit 1
not used
Bit 1
PGR 1
Bit 0
not used
(set to ’0’)
Bit 0
Bit 0
JTAG
Enable
Bit 0
PGR 0
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