PSD4235G2-12UIT STMICROELECTRONICS [STMicroelectronics], PSD4235G2-12UIT Datasheet - Page 50

• Manufacturer Part Number: PSD4235G2-12UIT
• Description: Flash in-system programmable (ISP) peripherals for 16-bit MCUs (3.3 V supply)
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Page register
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Page register
The 8-bit Page register increases the addressing capability of the MCU by a factor of up to
256. The contents of the register can also be read by the MCU. The outputs of the Page
register (PGR0-PGR7) are inputs to the DPLD decoder and can be included in the Sector
Select (FS0-FS7, CSBOOT0-CSBOOT3), and SRAM Select (RS0) equations.
If memory paging is not needed, or if not all eight page register bits are needed for memory
paging, these bits may be used in the CPLD for general logic. See Application Note
AN1154.
Table 5.14
connected to the internal data bus (D0-D7). The MCU can write to or read from the Page
register. The Page register can be accessed at address location CSIOP + E0h.
Figure 10. Page register
and
Figure 10
RESET
R/ W
D 0 - D 7
show the Page register. The eight flip-flops in the register are
D 0
D 1
D 2
D 3
D 4
D 5
D 6
D 7
REGISTER
PAGE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
PGR0
PGR1
PGR2
PGR3
PGR4
PGR5
PGR6
PGR7
DPLD
CPLD
AND
PLD
INTERNAL
SELECTS
AND LOGIC
PSD4235G2V
AI02871B