PSD4235G2-12UIT STMICROELECTRONICS [STMicroelectronics], PSD4235G2-12UIT Datasheet - Page 115
PSD4235G2-12UIT
Manufacturer Part Number
PSD4235G2-12UIT
Description
Flash in-system programmable (ISP) peripherals for 16-bit MCUs (3.3 V supply)
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
1.PSD4235G2-12UIT.pdf
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PSD4235G2V
Table 67.
1. Any input used to select an internal PSD function.
2. WR has the same timing as E, DS, LDS, UDS, WRL, and WRH signals.
3. tWHAX is 6 ns when writing to the output macrocell registers AB and BC.
4. tWHAX2 is the address hold time for DPLD inputs that are used to generate Sector Select signals for internal PSD memory.
5. Assuming WRITE is active before data becomes valid.
6. In multiplexed mode, latched address generated from ADIO delay to address output on any port.
7. Assuming data is stable before active WRITE signal.
Figure 46. Peripheral I/O read timing
t
t
t
t
Symbol
WHPV
DVMV
AVPV
WLMV
Trailing edge of WR to Port output
Valid Using I/O Port Data register
Data Valid to Port output Valid
Using macrocell register
Preset/Clear
Address input Valid to Address
Output Delay
WR Valid to Port output Valid Using
Macrocell register Preset/Clear
A /D BUS
ALE /AS
WRITE timing
CSI
RD
Parameter
ADDRESS
t AVQV (PF)
t SLQV (PF)
Conditions
t RLQV ( PF)
t RLRH (PF)
(2)(5)
(2)(7)
(2)
(6)
DATA ON PORT F
Min
t DVQV (PF)
DATA VALID
-90
Max
33
65
30
65
DC and AC parameters
t QXRH (PF)
t RHQZ (PF)
Min
-12
Max
33
68
35
70
AI05740
115/124
Unit
ns
ns
ns
ns
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