HYB18L256169BF QIMONDA [Qimonda AG], HYB18L256169BF Datasheet - Page 13

• Manufacturer Part Number: HYB18L256169BF
• Description: 256-Mbit Mobile-RAM
• Manufacturer: QIMONDA [Qimonda AG]

2.4
Table 6
Command
NOP
ACT
RD
WR
BST
PRE
ARF
MRS
–
–
1) DESELECT and NOP are functionally interchangeable.
2) BA0, BA1 provide bank address, and A0 - A12 provide row address.
3) BA0, BA1 provide bank address, A0 - A8 provide column address; A10 HIGH enables the Auto Precharge feature (non
4) This command is BURST TERMINATE if CKE is HIGH, DEEP POWER DOWN if CKE is LOW. The BURST TERMINATE
5) A10 LOW: BA0, BA1 determine which bank is precharged.
6) This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7) Internal refresh counter controls row and bank addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8) BA0, BA1 select either the Mode Register (BA0 = 0, BA1 = 0) or the Extended Mode Register (BA0 = 0, BA1 = 1); other
9) DQM LOW: data present on DQs is written to memory during write cycles; DQ output buffers are enabled during read
Address (A0 - A12, BA0, BA1), write data (DQ0 - DQ15) and command inputs (CKE, CS, RAS, CAS, WE, DQM)
are all registered on the positive edge of CLK.
commands and operations.
Figure 5
Data Sheet
persistent), A10 LOW disables the Auto Precharge feature.
command is defined for READ or WRITE bursts with Auto Precharge disabled only.
A10 HIGH: all banks are precharged and BA0, BA1 are “Don’t Care”.
combinations of BA0, BA1 are reserved; A0 - A12 provide the op-code to be written to the selected mode register.
cycles;
DQM HIGH: data present on DQs are masked and thus not written to memory during write cycles; DQ output buffers are
placed in High-Z state (two clocks latency) during read cycles.
DESELECT
NO OPERATION
ACTIVE (Select bank and row)
READ (Select bank and column and start read burst)
WRITE (Select bank and column and start write burst)
BURST TERMINATE or
DEEP POWER DOWN
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or
SELF REFRESH (enter self refresh mode)
MODE REGISTER SET
Data Write / Output Enable
Write Mask / Output Disable (High-Z)
Commands
Command Overview
Address / Command Inputs Timing Parameters
Figure 5
13
shows the basic timing parameters, which apply to all
CS RAS CAS WE DQM
H
L
L
L
L
L
L
L
L
–
–
H
H
H
H
X
L
L
–
L
L
–
X
H
H
H
H
L
L
L
L
–
–
HY[B/E]18L256169BF-7.5
X
H
H
H
H
L
L
L
L
–
–
256-Mbit Mobile-RAM
L/H
L/H
X
X
X
H
X
X
X
X
L
Functional Description
02032006-MP0M-7FQG
Bank / Row
Bank / Col
Bank / Col
Rev. 1.02, 2006-12
Address
Op-Code
Code
X
X
X
X
–
–
Notes
6)7)
1)
1)
2)
3)
3)
4)
5)
8)
9)
9)