LH28F160S5-L SHARP [Sharp Electrionic Components], LH28F160S5-L Datasheet - Page 8

• Manufacturer Part Number: LH28F160S5-L
• Description: 16 M-bit (2 MB x 8/1 MB x 16) Smart 5 Flash Memories (Fast Programming)
• Manufacturer: SHARP [Sharp Electrionic Components]

2 PRINCIPLES OF OPERATION
The LH28F160S5-L/S5H-L flash memories include
an on-chip WSM to manage block erase, full chip
erase, (multi) word/byte write and block lock-bit
configuration functions. It allows for : 100% TTL-
level control inputs, fixed power supplies during
block erase, full chip erase, (multi) word/byte write
and block lock-bit configuration, and minimal
processor overhead with RAM-like interface timings.
After initial device power-up or return from deep
power-down mode (see Table 2.1 and Table 2.2
"Bus Operations"), the device defaults to read
array mode. Manipulation of external memory
control pins allow array read, standby, and output
disable operations.
Status register, query structure and identifier codes
can be accessed through the CUI independent of
the V
successful block erase, full chip erase, (multi)
word/byte write and block lock-bit configuration. All
functions
contents—block erase, full chip erase, (multi)
word/byte write and block lock-bit configuration,
status, query and identifier codes—are accessed
via the CUI and verified through the status register.
Commands are written using standard micro-
processor write timings. The CUI contents serve as
input to the WSM, which controls the block erase,
full chip erase, (multi) word/byte write and block
lock-bit configuration. The internal algorithms are
regulated by the WSM, including pulse repetition,
internal verification, and margining of data.
Addresses and data are internally latched during
write cycles. Writing the appropriate command
outputs array data, accesses the identifier codes,
outputs query structure or outputs status register
data.
PP
voltage. High voltage on V
associated
with
altering
PP
memory
enables
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Interface software that initiates and polls progress
of block erase, full chip erase, (multi) word/byte
write and block lock-bit configuration can be stored
in any block. This code is copied to and executed
from system RAM during flash memory updates.
After successful completion, reads are again
possible via the Read Array command. Block erase
suspend allows system software to suspend a
block erase to read/write data from/to blocks other
than that which is suspended. Write suspend allows
system software to suspend a (multi) word/byte
write to read data from any other flash memory
array location.
2.1 Data Protection
Depending on the application, the system designer
may choose to make the V
switchable (available only when block erase, full
chip erase, (multi) word/byte write and block lock-bit
configuration are required) or hardwired to V
The device accommodates either design practice
and encourages optimization of the processor-
memory interface.
When V
altered. The CUI, with multi-step block erase, full
chip erase, (multi) word/byte write and block lock-bit
configuration
protection from unwanted operations even when
high voltage is applied to V
are disabled when V
voltage V
block
protection from inadvertent code or data alteration
by gating block erase, full chip erase and (multi)
word/byte write operations.
locking
PP
LKO
≤ V
or when RP# is at V
PPLK
command
capability
, memory contents cannot be
CC
is below the write lockout
LH28F160S5-L/S5H-L
sequences,
PP
provides
. All write functions
PP
IL
power supply
. The device’s
additional
provides
PPH1
.