LH28F160S5-L SHARP [Sharp Electrionic Components], LH28F160S5-L Datasheet - Page 10

• Manufacturer Part Number: LH28F160S5-L
• Description: 16 M-bit (2 MB x 8/1 MB x 16) Smart 5 Flash Memories (Fast Programming)
• Manufacturer: SHARP [Sharp Electrionic Components]

3.5 Read Identifier Codes Operation
The read identifier codes operation outputs the
manufacture code, device code, block status codes
for each block (see Fig. 2). Using the manufacture
and
automatically match the device with its proper
algorithms. The block status codes identify locked
or unlocked block setting and erase completed or
erase uncompleted condition.
3.6 Query Operation
The query operation outputs the query structure.
Query database is stored in the 48-byte ROM.
Query structure allows system software to gain
critical information for controlling the flash
Fig. 2 Device Identifier Code Memory Map
1FFFFF
1F0006
1F0005
1F0004
1F0003
1F0000
1EFFFF
020000
01FFFF
010006
010005
010004
010003
010000
00FFFF
000006
000005
000004
000003
000002
000001
000000
device
codes,
Future Implementation
Future Implementation
Future Implementation
Future Implementation
Future Implementation
Block 31 Status Code
(Blocks 2 through 30)
Block 1 Status Code
Block 0 Status Code
Manufacture Code
Reserved for
Reserved for
Reserved for
Reserved for
Reserved for
Device Code
the
system
Block 31
Block 1
Block 0
CPU
can
- 10 -
component. Query structures are always presented
on the lowest-order data output (DQ
3.7 Write
Writing commands to the CUI enable reading of
device data and identifier codes. They also control
inspection and clearing of the status register. When
V
controls block erase, full chip erase, (multi)
word/byte write and block lock-bit configuration.
The Block Erase command requires appropriate
command data and an address within the block to
be erased. The Word/Byte Write command requires
the command and address of the location to be
written. Set Block Lock-Bit command requires the
command and block address within the device
(Block Lock) to be locked. The Clear Block Lock-
Bits command requires the command and address
within the device.
The CUI does not occupy an addressable memory
location. It is written when WE# and CE# are
active. The address and data needed to execute a
command are latched on the rising edge of WE# or
CE# (whichever goes high first). Standard
microprocessor write timings are used. Fig. 17 and
Fig. 18 illustrate WE# and CE#-controlled write
operations.
4 COMMAND DEFINITIONS
When the V
from the status register, identifier codes, query, or
blocks are enabled. Placing V
successful block erase, full chip erase, (multi)
word/byte write and block lock-bit configuration
operations.
Device operations are selected by writing specific
commands into the CUI. Table 3 defines these
commands.
CC =
V
CC1/2
PP
and V
voltage ≤ V
PP =
V
PPH1
LH28F160S5-L/S5H-L
PPLK
, the CUI additionally
PPH1
, read operations
on V
0
-DQ
PP
7
) only.
enables