LH28F160S5-L SHARP [Sharp Electrionic Components], LH28F160S5-L Datasheet - Page 19

• Manufacturer Part Number: LH28F160S5-L
• Description: 16 M-bit (2 MB x 8/1 MB x 16) Smart 5 Flash Memories (Fast Programming)
• Manufacturer: SHARP [Sharp Electrionic Components]

4.8 Word/Byte Write Command
Word/byte write is executed by a two-cycle
command sequence. Word/Byte Write setup
(standard 40H or alternate 10H) is written, followed
by a second write that specifies the address and
data (latched on the rising edge of WE#). The
WSM then takes over, controlling the word/byte
write and write verify algorithms internally. After the
word/byte write sequence is written, the device
automatically outputs status register data when
read (see Fig. 5). The CPU can detect the
completion of the word/byte write event by
analyzing the STS pin or status register bit SR.7.
When word/byte write is complete, status register
bit SR.4 should be checked. If word/byte write error
is detected, the status register should be cleared.
The internal WSM verify only detects errors for "1"s
that do not successfully write to "0"s. The CUI
remains in read status register mode until it
receives another command.
Reliable word/byte writes can only occur when V
=
high voltage, memory contents are protected
against word/byte writes. If word/byte write is
attempted while V
SR.3 and SR.4 will be set to "1". Successful
word/byte write requires that the corresponding
block lock-bit be cleared or, if set, that WP# = V
If word/byte write is attempted when the
corresponding block lock-bit is set and WP# = V
SR.1 and SR.4 will be set to "1". Word/byte write
operations with V
results and should not be attempted.
4.9 Multi Word/Byte Write Command
Multi word/byte write is executed by at least four-
cycle or up to 35-cycle command sequence. Up to
32 bytes in x8 mode (16 words in x16 mode) can
be loaded into the buffer and written to the flash
array. First, multi word/byte write setup (E8H) is
written with the write address. At this point, the
V
CC1/2
and V
PP =
IL
PP
< WP# < V
V
PPH1
≤ V
PPLK
. In the absence of this
, status register bits
IH
produce spurious
CC
IH
IL
- 19 -
.
,
device automatically outputs extended status
register data (XSR) when read (see Fig. 6 and
Fig. 7). If extended status register bit XSR.7 is 0,
no Multi Word/Byte Write command is available and
multi word/byte write setup which just has been
written is ignored. To retry, continue monitoring
XSR.7 by writing multi word/byte write setup with
write address until XSR.7 transitions to "1". When
XSR.7 transitions to "1", the device is ready for
loading the data to the buffer. A word/byte count
(N)–1 is written with write address. After writing a
word/byte count (N)–1, the device automatically
turns back to output status register data. The
word/byte count (N)–1 must be less than or equal
to 1FH in x8 mode (0FH in x16 mode). On the next
write, device start address is written with buffer
data. Subsequent writes provide additional device
address and data, depending on the count. All
subsequent address must lie within the start
address plus the count. After the final buffer data is
written, write confirm (D0H) must be written. This
initiates WSM to begin copying the buffer data to
the flash array. An invalid Multi Word/Byte Write
command sequence will result in both status
register bits SR.4 and SR.5 being set to "1". For
additional multi word/byte write, write another multi
word/byte write setup and check XSR.7. The Multi
Word/Byte Write command can be queued while
WSM is busy as long as XSR.7 indicates "1",
because LH28F160S5-L/S5H-L have two buffers. If
an error occurs while writing, the device will stop
writing and flush next Multi Word/Byte Write
command loaded in Multi Word/Byte Write
command. Status register bit SR.4 will be set to "1".
No Multi Word/Byte Write command is available if
either SR.4 or SR.5 is set to "1". SR.4 and SR.5
should be cleared before issuing Multi Word/Byte
Write command. If a Multi Word/Byte Write
command is attempted past an erase block
boundary, the device will write the data to flash
array up to an erase block boundary and then stop
writing. Status register bits SR.4 and SR.5 will be
set to "1".
LH28F160S5-L/S5H-L